Faceted epitaxial source/drain regions
The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.
1. A structure, comprising:
a gate structure located on a substrate;
an L-shaped sidewall spacer directly contacting sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and
faceted diffusion regions on a top surface of the substrate, adjacent to the L-shaped sidewall spacer, wherein
the L-shaped sidewall spacer is composed of a tri-layer of material, and
wherein the tri-layer of material includes a recessed middle layer of material and an outer layer of sidewall material directly on the recessed middle layer, wherein the recessed middle layer is recessed on an upper portion thereof and is recessed with respect to the outer layer and the L-shaped sidewall spacer, and both the recessed middle layer and the outer layer are above and not in contact with a leg extending outwardly from a vertical section of the L-shaped sidewall spacer.
2. The structure of claim 1 , wherein the L-shaped sidewall spacer is composed of a low-k material directly contacting a top surface of diffusion regions in the substrate and extending onto sidewalls and a top portion of an adjacent gate structure.
3. The structure of claim 2 , wherein the L-shaped sidewall spacer is composed of a nitride material.
4. The structure of claim 3 , wherein the L-shaped sidewall spacer is composed of SiN or SiBCN.
5. The structure of claim 1 , wherein the recessed middle layer of material is different than an inner layer and the outer layer of sidewall material of the tri-layer of material, and the faceted diffusion regions do not contact the outer layer of sidewall material.
6. The structure of claim 5 , wherein the inner layer and the outer layer of the tri-layer of material is composed of a low-k spacer including a combination of SiBCN, SiN or SiOCN and the recessed middle layer of material is an oxide material.
7. The structure of claim 1 , wherein the faceted diffusion regions are epitaxial grown source and drain regions directly on the surface of the substrate, and which contacts a leg portion of the L-shaped sidewall spacer and is remote from a vertical section of the L-shaped sidewall spacer.
8. The structure of claim 1 , wherein the substrate is fully depleted Si material.
9. The structure of claim 1 , wherein the substrate is SiGe material and the gate structure is a PFET device.
10. A structure comprising:
a semiconductor on insulator substrate;
a gate structure formed on the semiconductor on insulator substrate;
an L-shaped sidewall spacer on a sidewall of the gate structure and extending above and remote from the semiconductor on insulator substrate; and
faceted raised epitaxial grown source and drain regions adjacent to and underneath a leg of the L-shaped sidewall spacer extending onto a surface of the semiconductor on insulator substrate,
wherein the L-shaped sidewall spacer is composed of a tri-layer of material comprising a middle layer of material directly underneath the L-shaped sidewall spacer and also extending above and remote from a surface of the semiconductor on insulator substrate, an inner layer of sidewall material directly underneath the middle layer of material and contacting the gate structure, the inner layer of sidewall material extends to and is in contact with the semiconductor on insulator substrate, and the faceted raised epitaxial grown source and drain regions are underneath the middle layer of material and the L-shaped sidewall spacer.
11. The structure of claim 10 , wherein the faceted diffusion regions are raised epitaxial source and drain regions.
12. The structure of claim 10 , wherein the L-shaped sidewall spacer is composed of a low-k spacer including SiBCN or SiN or SiOCN.
13. The structure of claim 10 , wherein an inner layer and the outer layer of the tri-layer of material are composed of a combination of SiBCN, SiN or SiOCN and the recessed middle layer of material is an oxide material.
14. The structure of claim 10 , wherein the semiconductor on insulator substrate is fully depleted Si material.
15. The structure of claim 10 , wherein the semiconductor on insulator substrate is SiGe material and the gate structure is a PFET device.
16. A method comprising:
forming a gate structure on a substrate;
forming at least a bi-layer spacer stack composed of a sacrificial layer of material;
etching the bi-layer spacer stack to form two L-shaped spacers comprising an L-shaped sidewall spacer directly on a sidewall of the gate structure and a L-shaped spacer composed of the sacrificial layer of material and which is directly on the L-shaped sidewall spacer;
removing at least a portion of the L-shaped spacer composed of the sacrificial layer, leaving the L-shaped sidewall spacer directly on the sidewall of the gate structure; and
forming a raised source/drain region on a surface of diffusion regions of the substrate adjacent to the first L-shaped sidewall spacer.
17. The method of claim 16 , wherein the bi-layer spacer stack is a tri-layer stack of material and the removing step includes a recess of a middle layer of the tri-layer stack of material to form the L-shaped sidewall spacer with three layers of material on a sidewall of the gate structure.