IP Library › Granted Patent US 12,414,348
Granted Patent B2
US 12,414,348 · App. 17/878,812 · Granted Sep 9, 2025

Insulated gate bipolar transistor

Inventor: Yoshihiro Ikura (Nagano, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H10D64/117H10D12/481H10D62/393H10D84/617
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,414,348
App. No.
17/878,812
Granted
Sep 9, 2025
Kind
B2
Abstract

An insulated gate bipolar transistor includes: a gate electrode embedded in a gate trench through a gate insulating film, the gate trench penetrating an emitter region and a base region; and a dummy electrode embedded in a dummy trench through a dummy insulating film, the dummy trench penetrating the emitter region and the base region and being disposed on each side of the gate trench and laterally spaced from each side of the gate trench so as to laterally face the gate trench through the base region, wherein the dummy electrode includes a bottom dummy conductive member disposed at a bottom of the dummy trench such that an upper surface of the bottom dummy conductive member is located lower than a lower surface of the base region, the bottom dummy conductive member being configured to be electrically connected to a gate potential.

Claims (19)

1. An insulated gate bipolar transistor, comprising:

a drift layer made of semiconductor of a first conductivity type;

a base region made of semiconductor of a second conductivity type on the drift layer;

an emitter region made of semiconductor of the first conductivity type on the base region, an impurity concentration of the emitter region being higher than that in the drift layer;

a gate electrode embedded in a gate trench through a gate insulating film, the gate trench penetrating the emitter region and the base region, the gate trench extending in a first direction in a plan view; and

a dummy electrode embedded in a dummy trench through a dummy insulating film, the dummy trench penetrating the emitter region and the base region and extending in parallel with the gate trench in the first direction in a plan view, the dummy trench being disposed on each side of the gate trench and laterally spaced from each side of the gate trench so as to laterally face the gate trench through the base region,

wherein the gate electrode is configured to be electrically connected to a gate potential, and

wherein the dummy electrode includes a bottom dummy conductive member disposed at a bottom of the dummy trench such that an upper surface of the bottom dummy conductive member is located lower than a lower surface of the base region, the bottom dummy conductive member being configured to be electrically connected to the gate potential.

2. The insulated gate bipolar transistor according to claim 1 , wherein the dummy electrode further includes an upper dummy conductive member that is disposed over the bottom dummy conductive member through a split insulating film, the upper dummy conductive member being configured to be electrically connected to an emitter potential.

3. The insulated gate bipolar transistor according to claim 1 , wherein the dummy trench further includes an upper embedded insulating film filles on the bottom dummy conductive member.

4. The insulated gate bipolar transistor according to claim 1 , wherein the gate electrode in the gate trench comprises a bottom gate conductive member at a bottom of the gate trench and an upper gate conductive member that is provided over the bottom gate conductive through an insulating film, an upper surface of the bottom gate conductive member being located lower than the lower surface of the base region.

5. The insulated gate bipolar transistor according to claim 1 , further comprising a trench bottom floating layer below the base region, the trench bottom floating layer covering the bottom of the dummy trench and being made of semiconductor of the second conductivity type second conductive type, an upper surface of the trench bottom floating layer being located higher than an upper surface of the bottom dummy conductive member in the dummy trench.

6. The insulated gate bipolar transistor according to claim 1 , further comprising an accumulation layer made of semiconductor of the first conductivity type below the base region.

7. The insulated gate bipolar transistor according to claim 1 , further comprising a diode having an anode region and a cathode region, the anode region being configured to be electrically connected to the gate potential, and the cathode region being electrically connected to the bottom dummy conductive member.

8. The insulated gate bipolar transistor according to claim 7 , further comprising a resistance element, one end of the resistance element being configured to be electrically connected to the gate potential, another end of the resistance element being electrically connected to the anode region of the diode and to the gate electrode.

9. The insulated gate bipolar transistor according to claim 1 , wherein the gate trench and the dummy trench are both provided in a plurality, and the plurality of the gate trenches and the plurality of the dummy trenches are arranged in a striped shape so as to be parallel to each other in the plan view.

10. The insulated gate bipolar transistor according to claim 1 ,

wherein the dummy electrode further includes an upper dummy conductive member that is disposed over the bottom dummy conductive member through a split insulating film, the upper dummy conductive member being configured to be electrically connected to an emitter potential, and

wherein the gate electrode in the gate trench comprises a bottom gate conductive member at a bottom of the gate trench and an upper gate conductive member that is provided over the bottom gate conductive through a split insulating film, an upper surface of the bottom gate conductive member being located lower than the lower surface of the base region, the bottom gate conductive member and the upper gate conductive member being both configured to be electrically connected to the gate potential.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2022
From: IKURA, YOSHIHIRO
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 060690/0259 →
Priority Claims (1)
JP 2021-146153 · Sep 8, 2021 · national
Continuity (1)
Related Publication 20230072478A1 · Mar 9, 2023
References Cited (13)
US 20180323294A1 · Okuda et al. · 2018 [cited by applicant]
US 20190027472A1 · Naito · 2019 [cited by examiner]
US 20190088769A1 · Matsushita · 2019 [cited by applicant]
US 20200144403A1 · Nishi · 2020 [cited by examiner]
US 20220157976A1 · Konishi et al. · 2022 [cited by applicant]
JP 2017147431A · 2017 [cited by applicant]
JP 2019057702A · 2019 [cited by applicant]
JP 202077727A · 2020 [cited by applicant]
JP 2022078755A · 2022 [cited by applicant]
WO 2017126167A1 · 2017 [cited by applicant]
WO 2018074427A1 · 2018 [cited by applicant]
K. Nishi et al., “CSTBT(TM) Based Split-Gate RC-IGBT with Low Loss and EMI Noise”, Proceedings of the 32nd International Symposium on Power Semiconductor Devices & ICs (ISPSD), Sep. 2020, pp. 138-141 (Mentioned on parag… [cited by applicant]
Japanese Office Action dated Apr. 30, 2025 in a counterpart Japanese patent application No. 2021-146153. (A machine translation (not reviewed for accuracy) attached.). [cited by applicant]