Sigma-delta analogue to digital converter
A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and a first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and a first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to a reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selection-switch connected in series between the first-feedback-node and the first terminal of the first-feedback-current-source; a second-feedback-selection-switch connected in series between the second-feedback-node and the first terminal of the second-feedback-current-source; and a third-feedback-selection-switch connected in series between the third-feedback-node and the first terminal of the first-feedback-current-source.
1. A sigma-delta ADC comprising:
a first-input-terminal configured to receive a first-analogue-input-signal;
a second-input-terminal configured to receive a second-analogue-input-signal;
a third-input-terminal configured to receive a third-analogue-input-signal;
a reference-terminal;
a first-amplifier-stage comprising:
a first-amplifier-first-input-terminal;
a first-amplifier-second-input-terminal;
a first-input-resistor connected in series between the first-input-terminal and a first-feedback-node;
a second-input-resistor connected in series between the second-input-terminal and a second-feedback-node;
a third-input-resistor connected in series between the third-input-terminal and a third-feedback-node;
a first-multiplexer-switch connected in series between the first-feedback-node and the first-amplifier-second-input-terminal;
a second-multiplexer-switch connected in series between the second-feedback-node and the first-amplifier-first-input-terminal;
a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal;
a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal;
a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal;
a first-feedback-selection-switch connected in series between the first-feedback-node and the first terminal of the first-feedback-current-source;
a second-feedback-selection-switch connected in series between the second-feedback-node and the first terminal of the second-feedback-current-source; and
a third-feedback-selection-switch connected in series between the third-feedback-node and the first terminal of the first-feedback-current-source.
2. The sigma-delta ADC of claim 1 , further including one or more:
even-input-terminals each configured to receive a respective even-analogue-input-signal;
even-input-resistors, each connected in series between a respective one of the even-input-terminals and a respective even-feedback-node;
even-multiplexer-switches, each connected in series between a respective one of the even-feedback-nodes and the first-amplifier-second-input-terminal; and
even-feedback-selection-switches, each connected in series between a respective one of the even-feedback-nodes and the first terminal of the first-feedback-current-source.
3. The sigma-delta ADC of claim 2 , further including one or more:
odd-input-terminals each configured to receive a respective odd-analogue-input-signal;
odd-input-resistors, each connected in series between a respective one of the odd-input-terminals and a respective odd-feedback-node;
odd-multiplexer-switches, each connected in series between a respective one of the odd-feedback-nodes and the first-amplifier-first-input-terminal; and
odd-feedback-selection-switches, each connected in series between a respective one of the odd-feedback-nodes and the first terminal of the second-feedback-current-source.
4. The sigma-delta ADC of claim 1 , further including one or more:
odd-input-terminals each configured to receive a respective odd-analogue-input-signal;
odd-input-resistors, each connected in series between a respective one of the odd-input-terminals and a respective odd-feedback-node;
odd-multiplexer-switches, each connected in series between a respective one of the odd-feedback-nodes and the first-amplifier-first-input-terminal; and
odd-feedback-selection-switches, each connected in series between a respective one of the odd-feedback-nodes and the first terminal of the second-feedback-current-source.
5. The sigma-delta ADC of claim 1 , wherein:
the first-multiplexer-switch is connected in series between the first-feedback-node and an even-amplifier-connection-node;
the second-multiplexer-switch is connected in series between the second-feedback-node and an odd-amplifier-connection-node;
a third-multiplexer-switch connected in series between the third-feedback-node and the even-amplifier-connection-node;
the sigma-delta ADC further comprising:
a first-even-amplifier-connection-switch connected in series between the even-amplifier-connection-node and the first-amplifier-second-input-terminal;
a second-even-amplifier-connection-switch connected in series between the even-amplifier-connection-node and the first-amplifier-first-input-terminal;
a first-odd-amplifier-connection-switch connected in series between the odd-amplifier-connection-node and the first-amplifier-first-input-terminal; and
a second-odd-amplifier-connection-switch connected in series between the odd-amplifier-connection-node and the first-amplifier-second-input-terminal.
6. The sigma-delta ADC of claim 5 , wherein:
the first-feedback-selection-switch is connected in series between the first-feedback-node and an even-current-source-connection-node;
the second-feedback-selection-switch is connected in series between the second-feedback-node and an odd-current-source-connection-node;
a third-feedback-selection-switch connected in series between the third-feedback-node and the even-current-source-connection-node;
the sigma-delta ADC further comprising:
a first-even-current-source-connection-switch connected in series between the even-current-source-connection-node and the first-feedback-current-source;
a second-even-current-source-connection-switch connected in series between the even-current-source-connection-node and the second-feedback-current-source;
a first-odd-current-source-connection-switch connected in series between the odd-current-source-connection-node and the second-feedback-current-source; and
a second-odd-current-source-connection-switch connected in series between the odd-current-source-connection-node and the first-feedback-current-source.
7. The sigma-delta ADC of claim 6 , further comprising:
a first-feedback-switch connected in series between: i) the first-feedback-current-source; and ii) each of the first-even-current-source-connection-switch and the second-odd-current-source-connection-switch, such that the first-feedback-switch can selectively disconnect the first-feedback-current-source from the even-current-source-connection-node and the odd-current-source-connection-node; and
a second-feedback-switch connected in series between: i) the second-feedback-current-source; and ii) each of the second-even-current-source-connection-switch and the first-odd-current-source-connection-switch, such that the second-feedback-switch can selectively disconnect the second-feedback-current-source from the even-current-source-connection-node and the odd-current-source-connection-node.
8. The sigma-delta ADC of claim 5 , further including one or more:
even-input-terminals each configured to receive a respective even-analogue-input-signal;
even-input-resistors, each connected in series between a respective one of the even-input-terminals and a respective even-feedback-node;
even-multiplexer-switches, each connected in series between a respective one of the even-feedback-nodes and the first-amplifier-second-input-terminal; and
even-feedback-selection-switches, each connected in series between a respective one of the even-feedback-nodes and the first terminal of the first-feedback-current-source.
9. The sigma-delta ADC of claim 5 , further including one or more:
odd-input-terminals each configured to receive a respective odd-analogue-input-signal;
odd-input-resistors, each connected in series between a respective one of the odd-input-terminals and a respective odd-feedback-node;
odd-multiplexer-switches, each connected in series between a respective one of the odd-feedback-nodes and the first-amplifier-first-input-terminal; and
odd-feedback-selection-switches, each connected in series between a respective one of the odd-feedback-nodes and the first terminal of the second-feedback-current-source.
10. The sigma-delta ADC of claim 5 , wherein the reference-terminal is connected to a negative reference voltage.
11. The sigma-delta ADC of claim 5 , wherein the sigma-delta ADC is a continuous time sigma-delta ADC.
12. A battery management system for a vehicle, wherein the battery management system comprises the sigma-delta ADC of claim 5 .
13. The sigma-delta ADC of claim 1 :
further including one or more:
even-input-terminals each configured to receive a respective even-analogue-input-signal;
even-input-resistors, each connected in series between a respective one of the even-input-terminals and a respective even-feedback-node;
even-multiplexer-switches, each connected in series between a respective one of the even-feedback-nodes and the first-amplifier-second-input-terminal; and
even-feedback-selection-switches, each connected in series between a respective one of the even-feedback-nodes and the first terminal of the first-feedback-current-source;
odd-input-terminals each configured to receive a respective odd-analogue-input-signal;
odd-input-resistors, each connected in series between a respective one of the odd-input-terminals and a respective odd-feedback-node;
odd-multiplexer-switches, each connected in series between a respective one of the odd-feedback-nodes and the first-amplifier-first-input-terminal; and
odd-feedback-selection-switches, each connected in series between a respective one of the odd-feedback-nodes and the first terminal of the second-feedback-current-source;
wherein:
the first-multiplexer-switch is connected in series between the first-feedback-node and an even-amplifier-connection-node;
the second-multiplexer-switch is connected in series between the second-feedback-node and an odd-amplifier-connection-node;
a third-multiplexer-switch connected in series between the third-feedback-node and the even-amplifier-connection-node;
the sigma-delta ADC further comprising:
a first-even-amplifier-connection-switch connected in series between the even-amplifier-connection-node and the first-amplifier-second-input-terminal;
a second-even-amplifier-connection-switch connected in series between the even-amplifier-connection-node and the first-amplifier-first-input-terminal;
a first-odd-amplifier-connection-switch connected in series between the odd-amplifier-connection-node and the first-amplifier-first-input-terminal;
a second-odd-amplifier-connection-switch connected in series between the odd-amplifier-connection-node and the first-amplifier-second-input-terminal;
the first-feedback-selection-switch is connected in series between the first-feedback-node and an even-current-source-connection-node;
the second-feedback-selection-switch is connected in series between the second-feedback-node and an odd-current-source-connection-node;
a third-feedback-selection-switch connected in series between the third-feedback-node and the even-current-source-connection-node;
the sigma-delta ADC further comprising:
a first-even-current-source-connection-switch connected in series between the even-current-source-connection-node and the first-feedback-current-source;
a second-even-current-source-connection-switch connected in series between the even-current-source-connection-node and the second-feedback-current-source;
a first-odd-current-source-connection-switch connected in series between the odd-current-source-connection-node and the second-feedback-current-source;
a second-odd-current-source-connection-switch connected in series between the odd-current-source-connection-node and the first-feedback-current-source;
each of the even-multiplexer-switches is connected in series between the respective one of the even-feedback-nodes and the even-amplifier-connection-node;
each of the odd-multiplexer-switches is connected in series between the respective one of the odd-feedback-nodes and the odd-amplifier-connection-node;
each of the even-feedback-selection-switches is connected in series between the respective one of the even-feedback-nodes and the even-current-source-connection-node; and
each of the odd-feedback-selection-switches is connected in series between the respective one of the odd-feedback-nodes and the odd-current-source-connection-node.
14. The sigma-delta ADC of claim 1 , wherein the reference-terminal is connected to a negative reference voltage.
15. The sigma-delta ADC of claim 1 , wherein the sigma-delta ADC is a continuous time sigma-delta ADC.
16. A battery management system for a vehicle, wherein the battery management system comprises the sigma-delta ADC of claim 1 .
17. A vehicle comprising the battery management system of claim 16 .