IP Library Granted Patent US 12,419,081
Granted Patent B2
US 12,419,081 · App. 17/510,392 · Granted Sep 16, 2025

Silicon-on-insulator substrate and method of manufacturing the same

Inventors: Chunyuan Qi (Singapore, SG); Sheng Zhang (Singapore, SG); Xingxing Chen (Singapore, SG); Chien-Kee Pang (Singapore, SG)
Assignee: UNITED MICROELECTRONICS CORP.
H10D30/6744H10D30/751H10D62/83
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Quick Facts
Patent No.
US 12,419,081
App. No.
17/510,392
Granted
Sep 16, 2025
Kind
B2
Abstract

An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.

Claims (10)

1. A method of manufacturing a silicon-on-insulator substrate, comprising:

forming a carbon-doped polysilicon trap-rich layer on a handler;

forming an organosilane-based oxide layer on said carbon-doped polysilicon trap-rich layer;

bonding a surface of a bulk silicon wafer directly on a surface of said organosilane-based oxide layer, wherein said surface of said bulk silicon wafer has no insulating layer formed thereon, and said bonding comprises:

performing a plasma treatment to said surface of said bulk silicon wafer and said surface of said organosilane-based oxide layer; and

after bonding said surface of said bulk silicon wafer and said surface of said organosilane-based oxide layer, performing a heat treatment to form stronger bonding between said surface of said bulk silicon wafer and said surface of said organosilane-based oxide layer;

performing a thinning process and a trimming process to said bulk silicon wafer through a grinding process to form a monocrystalline silicon layer.

2. The method of manufacturing a silicon-on-insulator substrate of claim 1 , further comprising performing a chemical mechanical polishing process to said organosilane-based oxide layer before bonding said bulk silicon wafer.

3. The method of manufacturing a silicon-on-insulator substrate of claim 1 , wherein comprising performing a carbon doping process to said a polysilicon trap-rich layer to form said carbon-doped polysilicon trap-rich layer.

4. The method of manufacturing a silicon-on-insulator substrate of claim 1 , wherein said handler is a silicon wafer or a glass substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2021
From: QI, CHUNYUAN; ZHANG, SHENG; CHEN, XINGXING; PANG, CHIEN-KEE
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 057906/0466 →
Priority Claims (1)
CN 202111119692.8 · Sep 24, 2021 · national
Continuity (1)
Related Publication 20230094739A1 · Mar 30, 2023
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