3D semiconductor wafer, devices, and structure
A 3D semiconductor wafer, the wafer including: a first device, where the first device includes a first level, the first level including first transistors, and where the first device includes a second level, the second level including first interconnections; a second device overlaying the first device, where the second device includes a third level, the third level including second transistors, and where the second device includes a fourth level, the fourth level including second interconnections, where the first device is substantially larger in area than the second device; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors.
1. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a trap-rich layer disposed between said first level and said second level; and
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,
wherein said plurality of connection paths comprises vertical connections connecting from said first interconnections to said second interconnections, and
wherein said vertical connections comprise through layer vias having a circumscribed diameter of less than 400 nm.
2. The device according to claim 1 , further comprising:
a shielding layer,
wherein said shielding layer provides protection for said first level from Electro Magnetic Interference (“EMI”) generated from at least said second level.
3. The device according to claim 1 , further comprising:
a thermal isolative layer disposed between said first level and said second level,
wherein said isolative layer has a thermal conductivity less than 0.5 W/m-K.
4. The device according claim 1 , further comprising:
a third level disposed underneath said trap-rich layer,
wherein said third level comprises a memory array.
5. The device according claim 1 , further comprising:
a third level disposed underneath said trap-rich layer,
wherein said third level comprises a first data bus,
wherein said first level comprises a second data bus, and
wherein said first data bus is connected to said second data bus.
6. The device according claim 1 , further comprising:
a third level disposed underneath said trap-rich layer,
wherein said third level comprises a memory array controlled by bitlines and wordlines, and
wherein at least one of said bitlines or wordlines is connected to at least one of said first transistors.
7. The device according claim 1 ,
wherein said third layer is a transferred layer,
wherein said transferred layer has been precisely thinned to less than 10 micron, and
wherein said precisely thinned is accomplished with use of a special layer to provide thinning control.
8. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a shielding layer disposed between said first level and said second level; and
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, and
wherein said shielding layer comprises providing protection for said first level from Electro Magnetic Interference (“EMI”) generated from said second level.
9. The device according to claim 8 ,
wherein said device comprises a trap-rich layer.
10. The device according to claim 8 , further comprising:
a thermal isolative layer disposed between said first level and said second level,
wherein said isolative layer has a thermal conductivity less than 0.5 W/m-K.
11. The device according claim 8 , further comprising:
a third level disposed underneath said trap-rich layer,
wherein said third level comprises a memory array.
12. The device according claim 8 , further comprising:
a third level disposed underneath said shielding layer,
wherein said third level comprises a first data bus,
wherein said first level comprises a second data bus, and
wherein said first data bus is connected to said second data bus.
13. The device according claim 8 ,
wherein said connections paths comprise vertical connections connecting from said first interconnection level to said second interconnections, and
wherein said vertical connections comprise through layer vias having a circumscribed diameter of less than 400 nm.
14. The device according claim 8 ,
wherein said third layer is a transferred layer,
wherein said transferred layer is precisely thinned to less than 10 micron, and
wherein said precisely thinned is accomplished with use of a special layer to provide thinning control.
15. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections,
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, and
wherein said second level comprises a first data bus,
wherein said first level comprise a second data bus, and
wherein said first data bus is connected to said second data bus.
16. The device according to claim 15 , the device comprising:
a third level,
wherein said third level comprises Radio Frequency (“RF”) circuits and a trap-rich layer.
17. The device according to claim 15 , further comprising:
a thermal isolative layer disposed between said first level and said second level,
wherein said isolative layer has a thermal conductivity less than 0.5 W/m-K.
18. The device according claim 15 , further comprising:
a third level disposed underneath said second level,
wherein said third level comprises a memory array.
19. The device according claim 15 , further comprising:
a third level comprising Radio Frequency (“RF”) circuits and a shielding layer,
wherein said shielding layer provides protection for said second level from Electro Magnetic Interference (“EMI”) generated from said third level.
20. The device according claim 15 ,
wherein said connections paths comprise vertical connections connecting from said first interconnections to said second interconnections, and
wherein said vertical connections comprise through layer vias having a circumscribed diameter of less than 400 nm.