Analog-cells-boundary region with buried power grid segment, semiconductor device including same and method of manufacturing same

1 . A semiconductor device comprising:

first and second active regions (ARs) having long axes extending in a first direction and being included correspondingly in first and second analog cell regions that abut relative to a second direction perpendicular to the first direction, a region where the first and second analog cell regions abut (analog-cell-boundary (ACB) region) extending from about a top boundary of the first AR to about a bottom boundary of the second AR;

pairs of gate segments, each pair including collinear first and second gate segments correspondingly over the first and second ARs, the first and second gate segments extending in the second direction;

metal-to-source/drain region (MD) contact structures correspondingly over the first and second ARs and interspersed with the pairs of gate segments, at least some of the MD contact structures being gap-spanning MD contact structures that extend continuously across a gap between the first and second ARs to overlie each of the first and second ARs;

via-to-PGBM_1st-segment contact structures (VBs) having long axes extending in the second direction, the VBs correspondingly being under the first or second ARs, the long axis of each VB and a short axis of each of the first and second ARs having about a same length; and

a PG segment in a first buried metallization (BM_1st) layer (PGBM_1st segment) under the VBs, the PGBM_1st segment underlapping a majority of each of the VBs, a midline of the PGBM_1st segment relative to the second direction (Y-midline) being at or proximal to a location where the first and second analog cell regions abut, the Y-midline of the PGBM_1st segment being at or proximal to a middle of the ACB region.

2 . The semiconductor device of claim 1 , further comprising:

via-to-gate contact structures (VGs) correspondingly over the first and second gate segments;

the VGs being free from overlying the first and second ARs; and

relative to proximal sides of the first and second ARs which are proximal to the gap, the VGs being adjacent to distal sides of the corresponding first and second ARs which are distal to the gap.

3 . The semiconductor device of claim 1 , further comprising:

a feedthrough via (FTV) extending in the first direction, being in the gap and being over the PGBM_1st segment.

4 . The semiconductor device of claim 3 , further comprising:

a via-to-MD (VD) rail (VDR) extending in the first direction, being in the gap and being correspondingly over the gap-spanning MD contact structures.

5 . The semiconductor device of claim 4 , wherein:

relative to the second direction, the VDR is substantially centered on the FTV.

6 . The semiconductor device of claim 1 , wherein:

relative to the first direction, the VBs align correspondingly with the gap-spanning MD contact structures.

7 . A semiconductor device comprising:

first and second active regions (ARs) having long axes extending in a first direction and being included correspondingly in first and second analog cell regions that abut relative to a second direction perpendicular to the first direction, a region where the first and second analog cell regions abut (analog-cell-boundary (ACB) region) extending from about a top boundary of the first AR to about a bottom boundary of the second AR;

pairs of gate segments, each pair including collinear first and second gate segments correspondingly over the first and second ARs, the first and second gate segments extending in the second direction;

first metal-to-source/drain region (MD) contact structures correspondingly over the first and second ARs and interspersed with the pairs of gate segments, at least some of the first MD contact structures being gap-spanning MD contact structures that extend continuously across a gap between the first and second ARs to overlie each of the first and second ARs;

a feedthrough via (FTV) extending in the first direction, being in the gap and under the MD contact structures, a midline of the FTV relative to the second direction (Y-midline) being at or proximal to a location where the first and second analog cell regions abut, the Y-midline of the FTV being at or proximal to a middle of the ACB region; and

a PG segment in a first buried metallization (BM_1st) layer (PGBM_1st segment) under the FTV.

8 . The semiconductor device of claim 7 ,

the PGBM_1st segment is free from underlapping each of the first and second ARs.

9 . The semiconductor device of claim 7 , further comprising:

a via-to-MD (VD) rail (VDR) extending in the first direction, being in the gap and being correspondingly over the gap-spanning MD contact structures.

10 . The semiconductor device of claim 9 , wherein:

the gap-spanning MD contact structures also overlie the VDR.

11 . The semiconductor device of claim 9 , wherein:

relative to the second direction, the VDR is substantially centered on the FTV.

12 . The semiconductor device of claim 7 , wherein:

relative to the first direction, each of the first and second gate segments is substantially a same width as each of the MD contact structures.

13 . The semiconductor device of claim 7 , further comprising:

via-to-gate contact structures (VGs) correspondingly over the first and second gate segments;

the VGs being free from overlying the first and second ARs; and

relative to proximal sides of the first and second ARs which are proximal to the gap, the VGs being adjacent to distal sides of the corresponding first and second ARs which are distal to the gap.

14 . The semiconductor device of claim 7 , further comprising:

second MD contact structures correspondingly over the FTV but being free from being over each of the first and second ARs.

15 . A semiconductor device comprising:

first and second active regions (ARs) having long axes extending in a first direction and being included correspondingly in first and second analog cell regions that abut relative to a second direction perpendicular to the first direction, a region where the first and second analog cell regions abut (analog-cell-boundary (ACB) region) extending from about a top boundary of the first AR to about a bottom boundary of the second AR;

pairs of gate segments, each pair including collinear first and second gate segments correspondingly over the first and second ARs, the first and second gate segments extending in the second direction;

metal-to-source/drain region (MD) contact structures correspondingly over the first and second ARs and interspersed with the pairs of gate segments, at least some of the MD contact structures being gap-spanning MD contact structures that extend continuously across a gap between the first and second ARs to overlie each of the first and second ARs;

via-to-PGBM_1st-segment contact structures (VBs) having long axes extending in the second direction, the VBs correspondingly being under the first or second ARs, the long axis of each VB and a short axis of each of the first and second ARs having about a same length;

a feedthrough via (FTV) extending in the first direction, being in the gap and under the MD contact structures, a midline of the FTV relative to the second direction being at or proximal to a location where the first and second analog cell regions abut, the midline of the FTV being at or proximal to a middle of the ACB region; and

a PG segment in a first buried metallization (BM_1st) layer (PGBM_1st segment) under the VBs and the FTV, the PGBM_1st segment underlapping a majority of each of the VBs, a midline of the PGBM_1st segment relative to the second direction being at or proximal to a location where the first and second analog cell regions abut, the midline of the PGBM_1st segment being at or proximal to a middle of the ACB region.

16 . The semiconductor device of claim 15 , wherein the VBs are offset from the FTV in the second direction.

17 . The semiconductor device of claim 15 , wherein the FTV underlaps none of the pairs of gate segments.

18 . The semiconductor device of claim 15 , wherein the PG segment has a variable dimension in the first direction.

19 . The semiconductor device of claim 15 , wherein the PG segment has a variable dimension in the second direction.

20 . The semiconductor device of claim 15 , wherein at least one gate segment of the pairs of gate segments overlaps the first AR and extends beyond a boundary of the first AR in the second direction.