Memory device and method of forming the same
Some embodiments relate to a memory device. The memory device includes a transistor having a first source/drain (S/D) region and a second S/D region, a first S/D contact disposed over the first S/D region, the first S/D contact extending lengthwise in a first direction, a second S/D contact disposed over the second S/D region, a first via landing on the first S/D contact, the first via extending lengthwise in a second direction different from the first direction, a second via landing on the second S/D contact, the first via having a length measured in the second direction that is larger than the second via, a first conductive line coupled to the first via, a second conductive line coupled to the second via, and a memory structure disposed above the transistor and coupled to the second conductive line.
1. A memory device, comprising:
a transistor having an active region that includes a first source/drain (S/D) region and a second S/D region;
a first S/D contact disposed over the first S/D region, wherein the first S/D contact extends lengthwise in a first direction and the active region extends lengthwise in a second direction different from the first direction, wherein along the first direction the first S/D contact extends beyond a boundary of the active region in a top view of the memory device;
a second S/D contact disposed over the second S/D region;
a first via disposed on the first S/D contact, wherein the first via extends lengthwise in the second direction different from the first direction;
a second via disposed on the second S/D contact, wherein the first via has a length measured in the second direction that is larger than the second via;
a first conductive line coupled to the first via;
a second conductive line coupled to the second via; and
a memory structure disposed above the transistor and coupled to the second conductive line.
2. The memory device of claim 1 , wherein the memory structure is a magnetic tunnel junction (MTJ).
3. The memory device of claim 2 , wherein the MTJ has a bottom electrode coupled to the second conductive line.
4. The memory device of claim 1 , wherein the first conductive line is directly above the first via, and the first conductive line extends lengthwise in the second direction.
5. The memory device of claim 4 , wherein the first conductive line has a width measured in the first direction larger than that of the first via.
6. The memory device of claim 1 , wherein the first S/D region is a source region, the second S/D region is a drain region, the first conductive line couples to a common source line of the memory device, and the second conductive line couples to a bit line of the memory device.
7. The memory device of claim 1 , wherein the transistor has a length measured in the second direction from an outer edge of the first S/D region to an outer edge of the second S/D region, and wherein the length of the first via is larger than the length of the transistor.
8. The memory device of claim 1 , wherein the second via has a width measured in the second direction that is larger than a width of the second S/D contact.
9. The memory device of claim 8 , wherein the width of the second via is larger than the width of the second S/D contact for about 5% to about 30%.
10. The memory device of claim 1 , wherein the first via and the first conductive line have a same length measured in the second direction.
11. A memory device, comprising:
an active region having a first source region, a second source region, and a drain region sandwiched between the first and second source regions;
a first gate structure disposed between the first source region and the drain region;
a second gate structure disposed between the second source region and the drain region;
a first contact coupled to the first source region and a second contact coupled to the second source region, wherein each of the first and second contacts extends lengthwise along a first direction;
a via extending lengthwise along a second direction that is different from the first direction, wherein the via is in contact with the first and second contacts;
a conductive line extending lengthwise along the second direction and across both the first and second gate structures in a top view of the memory device, wherein the conductive line interfaces a top surface of the via; and
a magnetic tunnel junction (MTJ) disposed above the active region, wherein the MTJ has an electrode coupled to the drain region.
12. The memory device of claim 11 , wherein the conductive line is directly above the via.
13. The memory device of claim 11 , wherein the via has a width measured in the first direction that is smaller than the conductive line.
14. The memory device of claim 13 , wherein the width of the via is about 40% to about 60% smaller than the conductive line.
15. The memory device of claim 11 , wherein the via is a first via, further comprising:
a third contact coupled to the drain region; and
a second via in contact with the third contact, wherein the second via has a width measured in the second direction that is larger than the third contact.
16. The memory device of claim 15 , wherein the first via is wider than the second via in the second direction.
17. A semiconductor device, comprising:
a continuous active region having a first source/drain (S/D) region, a second S/D region, and a third S/D region sandwiched between the first and second S/D regions along a first direction;
a first contact landing on the first S/D region;
a second contact landing on the second S/D region, wherein each of the first and second contacts extends lengthwise along a second direction perpendicular to the first direction;
a first via extending lengthwise along the first direction and coupled to the first and second contacts;
a third contact landing on the third S/D region;
a second via coupled to the third contact, wherein the first via has a length measured in the first direction that is larger than the second via; and
a magnetic tunnel junction (MTJ) coupled to the second via.
18. The semiconductor device of claim 17 , wherein the MTJ is disposed directly above the third S/D region.
19. The semiconductor device of claim 17 , further comprising:
a first gate structure disposed between the first and third S/D regions; and
a second gate structure disposed between the second and third S/D regions,
wherein the first and second gate structures are directly under the first via.
20. The semiconductor device of claim 17 , wherein in a cross-sectional view along the second direction, the first via has a top surface narrower than a bottom surface.