IP Library › Granted Patent US 12,424,601
Granted Patent B2
US 12,424,601 · App. 17/807,691 · Granted Sep 23, 2025

Semiconductor package and manufacturing method thereof

Inventors: Choongbin Yim (Seoul, KR); Jinwoo Park (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L25/18H01L21/563H01L23/3121H01L23/49811H01L24/16H01L24/29H01L24/32H01L24/73H01L24/92H01L2224/16227H01L2224/2929H01L2224/29386H01L2224/32225H01L2224/73204H01L2224/92125
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Quick Facts
Patent No.
US 12,424,601
App. No.
17/807,691
Granted
Sep 23, 2025
Kind
B2
Abstract

A semiconductor package includes: a package substrate; a semiconductor chip mounted above the package substrate; a chip connection terminal interposed between the semiconductor chip and the package substrate; an adhesive layer disposed on the package substrate and that covers a side and a top surface of the semiconductor chip and surrounds the chip connection terminal between the semiconductor chip and the package substrate; a molding layer disposed on the package substrate and that surrounds the adhesive layer; an interposer mounted on the adhesive layer and the molding layer, where the interposer includes an interposer substrate; and a conductive pillar disposed on the package substrate, where the conductive pillar surrounds the side of the semiconductor substrate, penetrates the molding layer in a vertical direction and connects the package substrate to the interposer substrate.

Claims (26)

1. A semiconductor package, comprising:

a package substrate;

a semiconductor chip mounted above the package substrate;

a chip connection terminal interposed between the semiconductor chip and the package substrate and that connects the semiconductor chip to the package substrate;

an adhesive layer disposed on the package substrate, wherein the adhesive layer covers a side and a top surface of the semiconductor chip and surrounds the chip connection terminal between the semiconductor chip and the package substrate;

a molding layer disposed on the package substrate and that surrounds the adhesive layer, wherein a material of the molding layer differs from a material of the adhesive layer so that a boundary surface forms where the molding layer and the adhesive layer contact each other;

an interposer mounted on the adhesive layer and the molding layer, wherein the interposer includes an interposer substrate; and

a conductive pillar disposed on the package substrate, wherein the conductive pillar surrounds the side of the semiconductor chip and penetrates the molding layer in a vertical direction and connects the package substrate to the interposer substrate.

2. The semiconductor package of claim 1 , wherein the adhesive layer comprises:

a first adhesive portion interposed between the package substrate and the semiconductor chip and that covers the chip connection terminal;

a second adhesive portion disposed adjacent to the side of the semiconductor chip; and

a third adhesive portion interposed between the semiconductor chip and the interposer substrate.

3. The semiconductor package of claim 2 , wherein

the interposer substrate includes a trench formed in a bottom portion of the interposer substrate that accommodates at least a portion of the adhesive layer, and

at least a portion of the third adhesive portion of the adhesive layer is disposed in the trench.

4. The semiconductor package of claim 1 , wherein the adhesive layer comprises a material that softens but does not completely dissolve or melt when heat is applied thereto.

5. The semiconductor package of claim 4 , wherein the adhesive layer comprises a die adhesive film (DAF).

6. The semiconductor package of claim 1 , wherein a top surface of the adhesive layer, a top surface of the molding layer, and a bottom surface of the interposer substrate are coplanar.

7. The semiconductor package of claim 1 , wherein

the interposer substrate comprises:

an interposer insulating layer;

an interposer substrate pattern that extends in the interposer insulating layer; and

the interposer further comprises:

a first interposer substrate pad disposed on a bottom surface of the interposer insulating layer, is connected to the interposer substrate pattern, and is in contact with the conductive pillar; and

a second interposer substrate pad disposed on the top surface of the interposer insulating layer and is connected to the interposer substrate pattern.

8. The semiconductor package of claim 7 , wherein the interposer further comprises a plurality of interposers between the bottom surface of the interposer substrate and the semiconductor chip and that are spaced apart in a horizontal direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2022
From: YIM, CHOONGBIN; PARK, JINWOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 060242/0714 →
Priority Claims (1)
KR 10-2021-0079517 · Jun 18, 2021 · national
Continuity (1)
Related Publication 20220406766A1 · Dec 22, 2022
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