IP Library › Granted Patent US 10,607,971

Granted Patent B2

US 10,607,971 · App. 15/968,143 · Granted Mar 31, 2020

Semiconductor package

Inventors: Yun Hyeok Im (Hwaseong-si, KR); Hee Seok Lee (Suwon-si, KR); Tae Woo Kang (Suwon-si, KR); Yeong Seok Kim (Seongnam-si, KR); Kyoung-Min Lee (Yongin-si, KR)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

H01L25/105 H01L23/3675 H01L23/3677 H01L23/49816 H01L23/49827 H01L23/5385 H01L23/5389 H01L2224/16225 H01L2224/32225 H01L2224/48091 H01L2224/48227 H01L2224/73265 H01L2225/1035 H01L2225/1058 H01L2225/1094 H01L2924/15311 H01L2924/181

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Quick Facts

Patent No.: US 10,607,971
App. No.: 15/968,143
Granted: Mar 31, 2020
Kind: B2

External Links

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Abstract

The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.

Claims (82)

1. A semiconductor package comprising:

a first semiconductor package comprising:

a first semiconductor package substrate; and

a first semiconductor chip disposed on the first semiconductor package substrate;

an interposer disposed on the first semiconductor package, wherein the interposer electrically connects the first semiconductor package with a second semiconductor package, the interposer comprising:

a first recess;

a first side; and

a second side opposite to the first side of the interposer, the second side being located between the first side and the first semiconductor package substrate, the first recess being provided in the second side of the interposer, the first recess including:

side walls extending from the second side toward the first side of the interposer; and

an upper surface of the first recess connected to the side walls, the upper surface of the first recess facing the first semiconductor chip;

a via disposed in the interposer, the via extending from the second side toward the first side of the interposer and disposed between the upper surface of the first recess and the first side of the interposer; and

a first connecting element provided on the first side of the interposer to electrically connect the first semiconductor package to the second semiconductor package,

wherein the via is configured to not transmit an electrical signal between the first semiconductor package and the second semiconductor package, and

wherein a gap is provided between the first semiconductor package and the second semiconductor package based on the first connecting element.

2. The semiconductor package of claim 1 , wherein at least a part of the first semiconductor chip is disposed in the first recess.

3. The semiconductor package of claim 1 , wherein the interposer further comprises an interposer hole penetrating from the recess upper surface to the first side of the interposer.

4. The semiconductor package of claim 3 , further comprising: a thermal interface material layer (TIM layer) disposed between the upper surface of the first recess and a first semiconductor chip upper surface, wherein the interposer hole is at least partially filled with the TIM layer.

5. The semiconductor package of claim 1 , wherein the interposer further comprises a second recess formed in the upper surface of the first recess, and wherein a first width of the first recess is greater than a second width of the second recess.

6. The semiconductor package of claim 1 , wherein the interposer further comprises a first pad disposed on the first side of the interposer, and a second pad disposed in the interposer and the second pad is spaced apart from the first pad and exposed through the first recess, and

wherein the via connects the first pad with the second pad.

7. The semiconductor package of claim 1 , further comprising: a thermal interface material layer (TIM layer) disposed between the upper surface of the first recess and an upper surface of the first semiconductor chip.

8. The semiconductor package of claim 1 , further comprising: a conductive material layer disposed between an upper surface of the first semiconductor chip and the upper surface of the first recess.

9. The semiconductor package of claim 1 , further comprising: a connecting element disposed on the first side of the interposer and overlapping with the via, wherein the connecting element is configured not to transmit an electrical signal between the second semiconductor package and the interposer.

10. The semiconductor package of claim 1 , further comprising:

an interposer connecting element disposed on the second side of the interposer and configured to transmit electrical signals between the interposer and the first semiconductor package substrate; and

a first pad disposed on the first side of the interposer and the first pad electrically connects the interposer connecting element with the second semiconductor package.

11. A semiconductor package comprising:

a first semiconductor package comprising:

a first semiconductor package substrate; and

a first semiconductor chip disposed on the first semiconductor package substrate;

an interposer disposed on the first semiconductor package, wherein the interposer electrically connects the first semiconductor package with a second semiconductor package, the interposer comprising:

a first recess;

a first side; and

a second side opposite to the first side, wherein the second side is located between the first side and the first semiconductor package substrate and the first recess is formed in the second side of the interposer, the first recess comprising:

side walls extending from the second side toward the first side of the interposer; and

an upper surface of the first recess connected to the side walls, and the upper surface of the first recess is disposed to face the first semiconductor chip;

an interposer connecting element disposed on the second side of the interposer and configured to transmit electrical signals between the interposer and the first semiconductor package substrate;

a first pad disposed on the first side of the interposer and electrically connecting the interposer connecting element with the second semiconductor package;

a via disposed in the interposer and extending from the second side toward the first side of the interposer, and disposed between the upper surface of the first recess and the first side of the interposer; and

a first connecting element provided on the first side of the interposer to electrically connect the first semiconductor package to the second semiconductor package,

wherein the via is configured to not transmit electrical signals between the first pad and the interposer connecting element, and

wherein a gap is provided between the first semiconductor package and the second semiconductor package based on the first connecting element.

12. The semiconductor package of claim 11 , further comprising:

a thermal interface material layer (TIM layer) disposed on the first side of the interposer.

13. The semiconductor package of claim 11 , further comprising:

a second pad disposed on the first side of the interposer, spaced apart from the first pad, connected to the via, and configured to not transmit electrical signals between the interposer and the second semiconductor package; and

an interposer insulating layer disposed between the second pad and the upper surface of the first recess,

wherein the first recess exposes the interposer insulating layer.

14. The semiconductor package of claim 11 , wherein the first semiconductor chip comprises a first chip portion, and a second chip portion protruding from the first chip portion,

wherein a first width of the first chip portion is greater than a second width of the second chip portion, and

wherein the first chip portion of the first semiconductor chip is disposed in the first recess.

15. The semiconductor package of claim 11 , wherein the first recess comprises a first recess portion having a first width and a second recess portion having a second width greater than the first width, and the first recess portion of the first recess comprises the upper surface of the first recess,

wherein the first semiconductor chip comprises a first chip portion, and a second chip portion protruding from the first chip portion,

wherein a first width of the first chip portion of the first semiconductor chip is greater than a second width of the second chip portion of the first semiconductor chip,

wherein the second chip portion of the first semiconductor chip is disposed in the first recess portion of the first recess, and

wherein at least a part of the first chip portion of the first semiconductor chip is disposed in the second recess portion of the first recess.

16. A semiconductor package comprising:

a first semiconductor package comprising:

a first semiconductor package substrate; and

a first semiconductor chip disposed on the first semiconductor package substrate;

a second semiconductor package comprising;

a second semiconductor package substrate; and

a second semiconductor chip disposed on the second semiconductor package substrate;

an interposer interposed between the first semiconductor package and the second semiconductor package and electrically connecting the first semiconductor package and the second semiconductor package, wherein the interposer comprises:

a first side; and

second side opposite to the first side, and the second side being located between the first side and the first semiconductor package substrate;

a first recess formed in the second side of the interposer, wherein the first recess comprises:

side walls extending from the second side toward the first side of the interposer;

an upper surface of the first recess connected to the side walls to face the first semiconductor chip;

a via disposed in the interposer and extending from the second side toward the first side of the interposer and disposed between the upper surface of the first recess and the first side of the interposer; and

a first connecting element provided on the first side of the interposer to electrically connect the first semiconductor package to the second semiconductor package,

wherein the via is configured to not transmit electrical signals between the first semiconductor package and the second semiconductor package, and

wherein a gap is provided between the first semiconductor package and the second semiconductor package based on the first connecting element.

17. The semiconductor package of claim 16 , wherein at least a part of the first semiconductor chip is disposed in the first recess.

18. The semiconductor package of claim 16 , wherein the interposer further comprises an interposer hole penetrating from the upper surface of the first recess to the first side of the interposer.

19. The semiconductor package of claim 16 , wherein the interposer further comprises a second recess formed in the upper surface of the first recess, and wherein a first width of the first recess is greater than a second width of the second recess.

20. The semiconductor package of claim 16 , further comprising:

a first connecting element disposed between the second semiconductor package substrate and the interposer,

wherein the first connecting element is configured to transmit electrical signals between the second semiconductor package and the interposer.

21. The semiconductor package of claim 20 , wherein the first connecting element is electrically disconnected from the via.

22. The semiconductor package of claim 11 , wherein the first connecting element is electrically disconnected from the via.

23. The semiconductor package of claim 16 , wherein the first connecting element is electrically disconnected from the via.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2018

From: IM, YUN HYEOK; LEE, HEE SEOK; KANG, TAE WOO; KIM, YEONG SEOK; LEE, KYOUNG-MIN

To: SAMSUNG ELECTRONICS CO., LTD.

Reel/Frame 045685/0124 →

Priority Claims (1)

KR 10-2017-0134688 · Oct 17, 2017 · national

Continuity (1)

Related Publication 20190115325A1 · Apr 18, 2019

Cited By (2)

US 12,424,601 US 12,616,045