Method for determining the phase difference between a first clock signal received by a first electronic component and a second clock signal received by a second electronic component
The invention relates to a method for determining the phase difference between a first clock signal (CK 1 ) received by a first electronic component (CE 1 ) and a second clock signal (CK 2 ) received by a second electronic component (CE 2 ), comprising the steps of: S 10 ) transmitting a first calibration signal (S 12 ); S 20 ) measuring a first delay (T 1 ); S 30 ) transmitting a second calibration signal (S 21 ); S 40 ) measuring a second delay (T 2 ); S 50 ) measuring the number (n) of clock pulses between the transmission of the first calibration signal (S 12 ) and the active edge of the first clock signal (CK 1 ) consecutive to the active edge of the second calibration signal (S 21 ); S 60 ) determining the phase difference depending on the parity of the number (n) of clock pulses.
1. A method for determining the phase difference between a first clock signal (CK 1 ) received by a first electronic component (CE 1 ) and a second clock signal (CK 2 ) received by a second electronic component (CE 2 ), the first clock signal (CK 1 ) and the second clock signal (CK 2 ) being generated synchronously and having an identical clock period (T c ), comprising the steps of:
S 10 ) transmitting by means of the first electronic component (CE 1 ) a first calibration signal (S 12 ) synchronously with the first clock signal (CK 1 );
S 20 ) measuring a first delay (T 1 ) between an active edge of the first calibration signal (S 12 ) and an active edge of the second clock signal (CK 2 ) consecutive to the active edge of the first calibration signal (S 12 );
S 30 ) transmitting by means of the second electronic component (CE 2 ) a second calibration signal (S 21 ) synchronously with the second clock signal (CK 2 );
S 40 ) measuring a second delay (T 2 ) between an active edge of the second calibration signal (S 21 ) and an active edge of the first clock signal (CK 1 ) consecutive to the active edge of the second calibration signal (S 21 );
S 50 ) measuring the number (n) of clock pulses between the transmission of the first calibration signal (S 12 ) and the active edge of the first clock signal (CK 1 ) consecutive to the active edge of the second calibration signal (S 21 ), the number (n) of clock pulses corresponding to a multiple of the clock period (T c );
S 60 ) determining the phase difference depending on the parity of the number (n) of clock pulses.
2. The method according to claim 1 , wherein:
T
ϕ
=
T
1
-
T
2
2
-
T
C
2
it n is odd
T
ϕ
=
T
1
-
T
2
2
n is even
where n corresponds to the number of clock pulses, T ϕ corresponds to the phase difference between the first clock signal (CK 1 ) and the second clock signal (CK 2 ), T 1 corresponds to the first delay, T 2 corresponds to the second delay, and T c corresponds to the clock period.
3. The method according to claim 1 , wherein the second calibration signal (S 21 ) is transmitted after a predetermined number of clock pulses consecutive to the first delay (T 1 ).
4. The method according to claim 1 , further comprising a step of correcting the phase difference between the first electronic component (CE 1 ) and the second electronic component (CE 2 ), depending on the phase difference determined in step S 60 ).
5. The method according to claim 1 , wherein the phase difference is determined periodically.
6. The method according to claim 1 , wherein the first calibration signal (S 12 ) is routed over a first line (L 1 ), the second calibration signal (S 21 ) is routed over a second line (L 2 ), the length of the first line (L 1 ) and the length of the second line (L 2 ) being equal.
7. The method according to claim 1 , wherein the first calibration signal (S 12 ) and the second calibration signal (S 21 ) are routed over the same bidirectional line, the second calibration signal (S 21 ) being delayed with respect to receipt of the first calibration signal (S 12 ) so as to avoid a conflict between the first calibration signal (S 12 ) and the second calibration signal (S 21 ).
8. A system for determining the phase difference between a first clock signal (CK 1 ) received by a first electronic component (CE 1 ) and a second clock signal (CK 2 ) received by a second electronic component (CE 2 ), the first clock signal (CK 1 ) and the second clock signal (CK 2 ) being generated synchronously and having an identical clock period (T c ), the system being configured to:
transmit by means of the first electronic component (CE 1 ) a first calibration signal (S 12 ) synchronously with the first clock signal (CK 1 );
measure a first delay (T 1 ) between an active edge of the first calibration signal (S 12 ) and an active edge of the second clock signal (CK 2 ) consecutive to the active edge of the first calibration signal (S 12 );
transmit by means of the second electronic component (CE 2 ) a second calibration signal (S 21 ) synchronously with the second clock signal (CK 2 );
measure a second delay (T 2 ) between an active edge of the second calibration signal (S 21 ) and an active edge of the first clock signal (CK 1 ) consecutive to the active edge of the second calibration signal (S 21 );
measure a number (n) of clock pulses between the first delay (T 1 ) and the second delay (T 2 ), the number (n) of clock pulses corresponding to a multiple of the clock period (T c );
determine a phase difference depending on the parity of the number (n) of clock pulses.
9. The system according to claim 8 , wherein:
T
ϕ
=
T
1
-
T
2
2
-
T
C
2
if n is odd
T
ϕ
=
T
1
-
T
2
2
if n is even
where n corresponds to the number of clock pulses, T ϕ corresponds to the phase difference between the first clock signal (CK 1 ) and the second clock signal (CK 2 ), T 1 corresponds to the first delay, T 2 corresponds to the second delay, and T c corresponds to the clock period.
10. The system according to claim 8 , wherein the first electronic component (CE 1 ) and the second electronic component (CE 2 ) are analogue-to-digital converters or digital-to-analogue converters.
11. An array antenna system, characterized in that it comprises at least one system for determining phase difference according to claim 8 .
12. The method according to claim 3 , further comprising a step of correcting the phase difference between the first electronic component (CE 1 ) and the second electronic component (CE 2 ), depending on the phase difference determined in step S 60 ).
13. The method according to claim 2 , further comprising a step of correcting the phase difference between the first electronic component (CE 1 ) and the second electronic component (CE 2 ), depending on the phase difference determined in step S 60 ).
14. The method according to claim 2 , wherein the second calibration signal (S 21 ) is transmitted after a predetermined number of clock pulses consecutive to the first delay (T 1 ).
15. The method according to claim 4 , wherein the phase difference is determined periodically.
16. The method according to claim 3 , wherein the phase difference is determined periodically.
17. The method according to claim 2 , wherein the phase difference is determined periodically.
18. The method according to claim 4 , wherein the first calibration signal (S 12 ) is routed over a first line (L 1 ), the second calibration signal (S 21 ) is routed over a second line (L 2 ), the length of the first line (L 1 ) and the length of the second line (L 2 ) being equal.
19. The method according to claim 3 , wherein the first calibration signal (S 12 ) is routed over a first line (L 1 ), the second calibration signal (S 21 ) is routed over a second line (L 2 ), the length of the first line (L 1 ) and the length of the second line (L 2 ) being equal.
20. The method according to claim 2 , wherein the first calibration signal (S 12 ) is routed over a first line (L 1 ), the second calibration signal (S 21 ) is routed over a second line (L 2 ), the length of the first line (L 1 ) and the length of the second line (L 2 ) being equal.