IP Library Granted Patent US 12,426,164
Granted Patent B2
US 12,426,164 · App. 18/650,160 · Granted Sep 23, 2025

Semiconductor package

Inventors: Masaya Toba (Tokyo, JP); Kazuhiko Kurafuchi (Tokyo, JP); Takashi Masuko (Tokyo, JP); Kazuyuki Mitsukura (Tokyo, JP); Shinichiro Abe (Tokyo, JP)
Assignee: RESONAC CORPORATION
H05K3/181B32B3/02B32B3/08C23C18/1605C23C18/165C23C18/20C23C18/32C23C18/38H05K1/032H05K2201/068
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Quick Facts
Patent No.
US 12,426,164
App. No.
18/650,160
Granted
Sep 23, 2025
Kind
B2
Abstract

A semiconductor package includes a wiring board and a semiconductor element mounted on the wiring board. The wiring board includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring. The metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass.

Claims (18)

1. A semiconductor package comprising:

a wiring board; and

a semiconductor element mounted on the wiring board;

wherein the wiring board comprises:

a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less;

a metal wiring provided on the surface of the first insulating material layer; and

a second insulating material layer provided to cover the metal wiring, wherein

the metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and

a nickel content rate of the metal layer is 0.25 to 20% by mass.

2. The semiconductor package according to claim 1 , wherein the nickel content rate of the metal layer is 3 to 20% by mass.

3. The semiconductor package according to claim 1 , wherein the nickel content rate of the metal layer is 0.25 to 3% by mass.

4. The semiconductor package according to claim 1 , wherein the first insulating material layer is composed of a cured product of a thermosetting resin composition.

5. The semiconductor package according to claim 1 , wherein the first insulating material layer is composed of a cured product of a photosensitive resin composition.

6. The semiconductor package according to claim 1 , further comprising a support substrate the first insulating layer being formed on,

wherein the support substrate is wafer-shaped and has a diameter of 200 mm, 300 mm or 450 mm.

7. The semiconductor package according to claim 1 , further comprising a support substrate the first insulating layer being formed on,

wherein the support substrate is rectangular panel-shaped and has a side of 300 to 700 mm.

8. The semiconductor package according to claim 1 , wherein the first insulating layer has a thermal expansion coefficient of 80×10 −6 /K or less.

Assignments (2)
CHANGE OF NAME Recorded May 2, 2024
From: SHOWA DENKO MATERIALS CO., LTD.
To: RESONAC CORPORATION
Reel/Frame 067291/0817 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2024
From: TOBA, MASAYA; KURAFUCHI, KAZUHIKO; MASUKO, TAKASHI; MITSUKURA, KAZUYUKI; ABE, SHINICHIRO
To: SHOWA DENKO MATERIALS CO., LTD.
Reel/Frame 067262/0944 →
Priority Claims (1)
JP 2018-238340 · Dec 20, 2018 · national
Continuity (2)
Continuation 17415041
Related Publication 20240306308A1 · Sep 12, 2024
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