Integrated circuitry comprising a memory array comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.
1. Integrated circuitry comprising a memory array comprising strings of memory cells, comprising:
an upper stack directly above a lower stack, the lower stack comprising vertically-alternating lower-conductive-tiers and lower-insulative-tiers, the upper stack comprising vertically-alternating upper-conductive-tiers and upper-insulative-tiers;
an upper tier of the lower-insulative-tiers or a lower tier of the upper-insulative-tiers comprising non-stoichiometric silicon dioxide having a silicon-to-oxygen atomic ratio greater than 0.5, a higher tier of the upper-insulative-tiers that is above said lower upper-insulative-tier comprising silicon dioxide having a silicon-to-oxygen atomic ratio less than or equal to 0.5; and
channel-material strings of memory cells extending through the upper stack and the lower stack including through the non-stoichiometric silicon dioxide.
2. The integrated circuitry of claim 1 wherein the non-stoichiometric silicon dioxide has silicon-to-oxygen atomic ratio no greater than 1.0.
3. The integrated circuitry of claim 1 wherein the upper tier of the lower-insulative-tiers comprises the non-stoichiometric silicon dioxide.
4. The integrated circuitry of claim 3 wherein the upper tier of the lower-insulative-tiers is the uppermost tier of the lower-insulative-tiers.
5. The integrated circuitry of claim 3 wherein multiple of the upper lower-insulative-tiers comprise the non-stoichiometric silicon dioxide.
6. The integrated circuitry of claim 1 wherein the lower tier of the upper-insulative-tiers comprises the non-stoichiometric silicon dioxide.
7. The integrated circuitry of claim 6 wherein the lower tier of the upper-insulative-tiers is the lowest tier of the upper-insulative-tiers.
8. The integrated circuitry of claim 6 wherein multiple of the lower upper-insulative-tiers comprise the non-stoichiometric silicon dioxide.
9. The integrated circuitry of claim 1 wherein each of the upper tiers of the lower-insulative-tiers and the lower tiers of the upper-insulative-tiers comprises the non-stoichiometric silicon dioxide.
10. Integrated circuitry comprising a memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the conductive tiers individually comprising a horizontally-elongated conductive line;
a second vertical stack aside the first vertical stack, the second vertical stack comprising an upper portion and a lower portion, the upper portion comprising alternating upper-first-insulating-tiers and upper-second-insulating-tiers of different composition relative one another, the lower portion comprising lower-first-insulating-tiers and lower-second-insulating-tiers of different composition relative one another; and
an upper tier of the lower-second-insulating-tiers or a lower tier of the upper-second-insulating-tiers comprising non-stoichiometric silicon dioxide having a silicon-to-oxygen atomic ratio greater than 0.5, a higher tier of the upper-second-insulating-tiers that is above said lower upper-second-insulating-tier comprising silicon dioxide having a silicon-to-oxygen atomic ratio less than or equal to 0.5.
11. The integrated circuitry of claim 10 wherein the non-stoichiometric silicon dioxide has silicon-to-oxygen atomic ratio no greater than 1.0.
12. The integrated circuitry of claim 10 wherein the upper tier of the lower-second-insulating-tiers comprises the non-stoichiometric silicon dioxide.
13. The integrated circuitry of claim 12 wherein the upper tier of the lower-second-insulating-tiers is the uppermost tier of the lower-second-insulating-tiers.
14. The integrated circuitry of claim 12 wherein multiple of the upper lower-second-insulating-tiers comprise the non-stoichiometric silicon dioxide.
15. The integrated circuitry of claim 10 wherein the lower tier of the upper-second-insulating-tiers comprises the non-stoichiometric silicon dioxide.
16. The integrated circuitry of claim 15 wherein the lower of the upper-second-insulating-tiers is the lowest tier of the upper-second-insulating-tiers.
17. The integrated circuitry of claim 15 wherein multiple of the lower upper-second-insulating-conductive-tiers comprise the non-stoichiometric silicon dioxide.
18. The integrated circuitry of claim 10 wherein each of the upper tiers of the lower-second-insulating-tiers and the lower tier of the upper-second-insulating-tiers comprises the non-stoichiometric silicon dioxide.