Semiconductor device, memory cell and method of forming the same

1. A memory cell, comprising:

a selector disposed over a substrate, wherein the selector comprises:

a bottom electrode;

an ovonic threshold switch layer on the bottom electrode;

an inter-electrode over the ovonic threshold switch layer; and

an intermediate layer between the ovonic threshold switch layer and the inter-electrode, wherein the intermediate layer has a curved sidewall extending from a top surface of the ovonic threshold switch layer to a bottom surface of the inter-electrode;

a memory element disposed on the selector; and

a connecting pad disposed on the memory element.

2. The memory cell of claim 1 , wherein the memory element comprises:

the inter-electrode;

a top electrode over the inter-electrode; and

a storage layer located between the inter-electrode and the top electrode.

3. The memory cell of claim 2 , wherein the intermediate layer comprises a metal material different from the inter-electrode.

4. The memory cell of claim 1 , wherein a width of the intermediate layer increases toward the bottom electrode.

5. The memory cell of claim 1 , wherein the curved sidewall is concave into the intermediate layer.

6. The memory cell of claim 1 , wherein a hydrophilicity of the intermediate layer is greater than a hydrophilicity of the ovonic threshold switch layer, and less than a hydrophilicity of the inter-electrode.

7. A semiconductor device, comprising:

a first interconnect structure disposed on a substrate;

a selector disposed on the first interconnect structure, wherein the selector comprises:

a bottom electrode;

an ovonic threshold switch layer on the bottom electrode;

an inter-electrode over the ovonic threshold switch layer;

an intermediate layer between the ovonic threshold switch layer and the inter-electrode, wherein the intermediate layer has a first curved sidewall, the first curved sidewall includes a first portion physically connected to a top surface of the ovonic threshold switch layer and a second portion between the first portion and the inter-electrode, the first portion of the first curved sidewall has a first included angle with respect to a normal direction of the substrate, and the first included angle is in a range of 30 degrees to 60 degrees; and

a memory element disposed on the selector;

a connecting pad disposed on the memory element; and

a second interconnect structure disposed on the memory element and electrically connected to the connecting pad.

8. The semiconductor device of claim 7 , wherein the memory element comprises:

the inter-electrode;

a top electrode over the inter-electrode; and

a storage layer located between the inter-electrode and the top electrode.

9. The semiconductor device of claim 8 , wherein the intermediate layer comprises a metal material while the bottom electrode, the inter-electrode and the top electrode comprise metal compound.

10. The semiconductor device of claim 9 , wherein the metal material of the intermediate layer comprises tungsten, and the bottom electrode, the inter-electrode and the top electrode comprise metal nitride.

11. The semiconductor device of claim 10 , wherein the memory element further comprises:

an adhesive layer located between the top electrode and the storage layer, and the adhesive layer is different from the intermediate layer.

12. The semiconductor device of claim 8 , wherein the inter-electrode has a second curved sidewall, the second curved sidewall of the inter-electrode includes a first portion physically connected to a top surface of the intermediate layer and a second portion between the first portion of the second curved sidewall and the storage layer, the first portion of the second curved sidewall has a second included angle with respect to the normal direction of the substrate, and the first included angle of the intermediate layer is greater than the second included angle of the inter-electrode.

13. The semiconductor device of claim 12 , wherein the ovonic threshold switch layer has a sidewall, the sidewall includes a first portion physically connected to a top surface of the first interconnect structure and a second portion between the first portion of the sidewall and the intermediate layer, the first portion of the sidewall has a third included angle with respect to the normal direction of the substrate, and the second included angle of the inter-electrode is greater than the third included angle of the ovonic threshold switch layer.

14. The semiconductor device of claim 7 , wherein a top width of the intermediate layer is equal to or smaller than a bottom width of the intermediate layer.

15. The semiconductor device of claim 7 , wherein a bottom width of the inter-electrode is smaller than a top width of the ovonic threshold switch layer.

16. The semiconductor device of claim 7 , wherein a hydrophobicity of the intermediate layer is greater than a hydrophobicity of the inter-electrode, and less than a hydrophobicity of the ovonic threshold switch layer.

17. A memory cell, comprising:

a selector disposed over a substrate, wherein the selector comprises:

a bottom electrode;

an ovonic threshold switch layer on the bottom electrode;

an intermediate layer on the ovonic threshold switch layer, wherein a width of the intermediate layer increases toward the ovonic threshold switch layer, the intermediate layer has an edge portion, and the edge portion is bent downwardly from a top surface of the ovonic threshold switch layer to cover a sidewall of the ovonic threshold switch layer;

an inter-electrode on the intermediate layer; and

a memory element disposed on the selector.

18. The memory cell of claim 17 , wherein the memory element comprises:

the inter-electrode;

a top electrode over the inter-electrode; and

a storage layer located between the inter-electrode and the top electrode.

19. The memory cell of claim 17 , wherein a width of the inter-electrode increases toward the ovonic threshold switch layer.

20. The memory cell of claim 17 , wherein the intermediate layer has curved sidewalls.