Gates structures of nanostructure field-effect transistors (nano-FETs) including a plurality of semiconductor based capping materials and methods of forming the same
View Patent ↗A semiconductor device includes nanosheets between the source/drain regions, and a gate structure over the substrate and between the source/drain regions, the gate structure including a gate dielectric material around each of the nanosheets, a work function material around the gate dielectric material, a first capping material around the work function material, a second capping material around the first capping material, wherein the second capping material is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheets, and a gate fill material over the second capping material.
1. A method of forming a semiconductor device, the method comprising:
forming a first nanosheet over a substrate;
forming a second nanosheet over the first nanosheet, wherein the first nanosheet and the second nanosheet are disposed between source/drain regions, the source/drain regions being disposed over the substrate;
depositing a gate dielectric material around each of the first nanosheet and the second nanosheet;
depositing a work function material around the gate dielectric material;
forming a first capping material around the work function material, wherein the first capping material comprises silicon, and wherein a gap is disposed between the first capping material around the first nanosheet and the first capping material around the second nanosheet;
oxidizing the first capping material; and
forming a gate fill material over the first nanosheet and the second nanosheet.
2. The method of claim 1 , wherein the first capping material has a thickness that is in a range from 5 Å to 30 Å.
3. The method of claim 1 , further comprising:
forming a second capping material around the first capping material, wherein the second capping material fills the gap, and wherein the first capping material is different from the second capping material.
4. The method of claim 3 , wherein the second capping material has a same material composition as the work function material.
5. The method of claim 3 , wherein the second capping material and the work function material comprise titanium nitride.
6. The method of claim 3 , wherein a thickness of the second capping material over a top surface of the second nanosheet is different from a thickness of the second capping material between a bottom surface of the second nanosheet and a top surface of the first nanosheet.
7. The method of claim 6 , wherein the thickness of the second capping material over the top surface of the second nanosheet is smaller than the thickness of the second capping material between the bottom surface of the second nanosheet and the top surface of the first nanosheet.
8. A method of forming a semiconductor device, the method comprising:
forming source/drain regions over a substrate;
forming a first nanowire and a second nanowire over the substrate, the first nanowire disposed between the substrate and the second nanowire, wherein each of the first nanowire and the second nanowire have a circular cross-section;
depositing a gate dielectric material around each of the first nanowire and the second nanowire;
depositing a work function material around the gate dielectric material;
forming a first capping material around the work function material;
forming a second capping material around the first capping material, wherein a composition of the work function material and a composition of the second capping material are the same; and
forming a gate fill material over the first nanowire and the second nanowire.
9. The method of claim 8 , further comprising:
before depositing the gate dielectric material, forming an interfacial dielectric material around each of the first nanowire and the second nanowire, wherein the gate dielectric material is different from the interfacial dielectric material.
10. The method of claim 9 , wherein the interfacial dielectric material comprises silicon oxide.
11. The method of claim 8 , wherein the first capping material comprises silicon.
12. The method of claim 8 , wherein the first capping material comprises silicon oxide.
13. The method of claim 8 , wherein the work function material and the second capping material each comprise titanium nitride, tantalum nitride, titanium aluminum nitride, titanium silicon nitride, titanium aluminum, tantalum aluminum, or a combination thereof.
14. The method of claim 8 , wherein the first capping material has a thickness that is in a range from 5 Å to 30 Å.
15. A semiconductor device comprising:
nanosheets between source/drain regions, the nanosheets and the source/drain regions being disposed over a substrate; and
a gate structure between the source/drain regions, the gate structure comprising:
a gate dielectric material around each of the nanosheets;
a work function material around the gate dielectric material;
a first capping material around the work function material, wherein the first capping material comprises a semiconductor material;
a second capping material around the first capping material, wherein the second capping material has a same composition as the work function material; and
a gate fill material over the second capping material.
16. The semiconductor device of claim 15 , further comprising an interfacial dielectric material around each of the nanosheets, wherein the interfacial dielectric material is disposed between each of the nanosheets and the gate dielectric material, and wherein the gate dielectric material is different from the interfacial dielectric material.
17. The semiconductor device of claim 16 , wherein the interfacial dielectric material comprises silicon oxide.
18. The semiconductor device of claim 15 , wherein the first capping material comprises silicon.
19. The semiconductor device of claim 18 , wherein a thickness of the first capping material is in a range from 5 Å to 30 Å.
20. The semiconductor device of claim 15 , wherein the work function material and the second capping material each comprise titanium nitride, tantalum nitride, titanium aluminum nitride, titanium silicon nitride, titanium aluminum, tantalum aluminum, or a combination thereof.