Reducing k values of dielectric films through anneal
A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl 3 ) 2 CH 2 ), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.
1. A method comprising:
forming a first semiconductor layer;
forming a second semiconductor layer over and contacting the first semiconductor layer;
laterally recessing the second semiconductor layer to form a lateral recess overlapping the first semiconductor layer; and
forming a low-k inner spacer in the lateral recess, wherein the forming the low-k inner spacer comprises:
depositing a high-k dielectric layer extending into the lateral recess; and
performing a treatment process to convert the high-k dielectric layer into a low-k dielectric layer; and
etching the low-k dielectric layer to remove portions of the low-k dielectric layer outside of the lateral recess.
2. The method of claim 1 , wherein the treatment process comprises:
performing an oxidation process on the high-k dielectric layer using oxygen (O 2 ) as a first process gas; and
after the oxidation process, performing a dry anneal process on the high-k dielectric layer.
3. The method of claim 2 , wherein the oxidation process is performed at a lower temperature than the dry anneal process.
4. The method of claim 2 , wherein the dry anneal process is performed using an oxygen-free process gas.
5. The method of claim 2 , wherein the dry anneal process is performed using nitrogen (N 2 ) as a second process gas.
6. The method of claim 1 , wherein the depositing the high-k dielectric layer comprises an atomic layer deposition cycle comprising:
pulsing and then purging calypso ((SiCl 3 ) 2 CH 2 ); and
pulsing and then purging ammonia.
7. The method of claim 6 further comprising repeating the atomic layer deposition cycle to increase a thickness of the high-k dielectric layer.
8. The method of claim 1 , wherein before the treatment process, the high-k dielectric layer has a first dielectric constant in a first range between 4.5 and 6.0, and after the treatment process, the low-k dielectric layer has a second dielectric constant in a second range between 3.5 and 3.8.
9. The method of claim 1 further comprising:
after the low-k inner spacer is formed, removing the second semiconductor layer to leave a space; and
forming a gate stack, wherein the gate stack extends into the space and encircles the first semiconductor layer.
10. A method comprising:
forming a stack of layers comprising:
a first silicon layer and a second silicon layer; and
a silicon germanium layer between the first silicon layer and the second silicon layer;
laterally recessing the silicon germanium layer to form a lateral recess;
depositing a dielectric layer, wherein the dielectric layer extends into the lateral recess;
annealing the dielectric layer to reduce k values of the dielectric layer;
trimming the dielectric layer to remove first portions of the dielectric layer outside of the lateral recesses, with second portions of the dielectric layer inside the recesses being left as inner spacers;
removing the silicon germanium layer; and
forming a gate stack extending into a space between the first silicon layer and the second silicon layer.
11. The method of claim 10 , wherein the dielectric layer is deposited through an atomic layer deposition process, with calypso ((SiCl 3 ) 2 CH 2 ) and ammonia being used as precursors.
12. The method of claim 11 further comprising, after depositing the dielectric layer, performing a wet anneal process and a dry anneal process on the dielectric layer.
13. The method of claim 12 , wherein the trimming the dielectric layer is performed after the wet anneal process and the dry anneal process are performed on the dielectric layer.
14. The method of claim 12 , wherein the trimming the dielectric layer is performed before the wet anneal process and the dry anneal process are performed on the dielectric layer.
15. The method of claim 12 , wherein the wet anneal process is performed at a first temperature, and the dry anneal process is performed at a second temperature higher than the first temperature.
16. A method comprising:
forming a stack of layers comprising:
a plurality of semiconductor nanostructures; and
a plurality of sacrificial layers, wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly;
laterally recessing the plurality of sacrificial layers to form lateral recesses;
depositing a dielectric layer extending into the lateral recesses, wherein the dielectric layer is deposited using calypso ((SiCl 3 ) 2 CH 2 ) and ammonia as precursors;
annealing the dielectric layer to reduce a k value of the dielectric layer;
removing portions of the dielectric layer outside of the lateral recesses;
removing the plurality of sacrificial layers to leave spaces; and
forming a gate stack, wherein portions of the gate stack are filled into the spaces.
17. The method of claim 16 , wherein the annealing the dielectric layer results in the dielectric layer to be converted from a high-k dielectric layer to a low-k dielectric layer.
18. The method of claim 16 , wherein the annealing comprises:
performing a first anneal process using oxygen (O 2 ) as a first process gas; and
after the first anneal process, performing a second anneal process on the dielectric layer using nitrogen (N 2 ) as a second process gas.
19. The method of claim 16 , wherein the annealing comprises a wet anneal process and a dry anneal process performed after the wet anneal process.
20. The method of claim 19 , wherein the wet anneal process is performed at a first temperature, and the dry anneal process is performed at a second temperature higher than the first temperature.