Semiconductor device including source/drain regions having triangular tip regions
A semiconductor device includes a substrate including a first region, a second region, and active regions extending in a first direction in the first region and in the second region; gate electrodes on the first region and the second region, the gate electrodes intersecting the active regions and extending in a second direction; a plurality of channel layers spaced apart from each other in a third direction on active regions of the active regions and encompassed by the gate electrodes, the third direction being perpendicular to an upper surface of the substrate; and first source/drain regions and second source/drain regions in portions of the active regions that are recessed on both sides of the gate electrodes, the first source/drain regions and the second source/drain regions being connected to the plurality of channel layers, wherein the first source/drain regions are in the first region, and the second source/drain regions are in the second region, wherein an end portion of each of the first source/drain regions in the second direction in a plan view includes a tip region protruding in the second direction, and wherein an end portion of each of the second source/drain regions in the second direction in the plan view extends flatly in the first direction.
1. A semiconductor device comprising:
a substrate comprising a first region, a second region, and active regions extending in a first direction in the first region and in the second region;
gate electrodes on the first region and the second region, the gate electrodes intersecting the active regions and extending in a second direction;
a plurality of channel layers spaced apart from each other in a third direction on the active regions and encompassed by the gate electrodes, the third direction being perpendicular to an upper surface of the substrate; and
first source/drain regions and second source/drain regions in portions of the active regions that are recessed on opposite sides of the gate electrodes, the first source/drain regions and the second source/drain regions being connected to the plurality of channel layers,
wherein the first source/drain regions are in the first region, and the second source/drain regions are in the second region,
wherein an end portion of each of the first source/drain regions in the second direction in a plan view comprises a tip region protruding in the second direction,
wherein an end portion of each of the second source/drain regions in the second direction in the plan view extends flatly in the first direction, and
wherein each tip region comprises a triangular region in the plan view that points in the second direction.
2. The semiconductor device of claim 1 , wherein each of the first source/drain regions and each of the second source/drain regions have a first length in the first direction and a second length, greater than the first length, in the second direction.
3. The semiconductor device of claim 2 , wherein, in the plan view, each of an end portion of each of the first source/drain regions and an end portion of each of the second source/drain regions in the first direction comprises a flat region extending flatly in the second direction, and
wherein a length of each flat region in the second direction is greater than the first length.
4. The semiconductor device of claim 1 , wherein the tip regions are positioned in a center of the first source/drain regions in the first direction.
5. The semiconductor device of claim 1 , wherein each of the plurality of channel layers has a third length in the second direction, and
wherein each of the first source/drain regions has a fourth length, greater than the third length, in the second direction.
6. The semiconductor device of claim 5 , wherein the third length is in a range of about 20 nm to about 50 nm.
7. The semiconductor device of claim 1 , further comprising:
a capping layer covering a surface of each of the first source/drain regions,
wherein, in the plan view, the capping layer covers each of the tip regions and extends to an outer side of each of the first source/drain regions.
8. The semiconductor device of claim 7 , further comprising an interlayer insulating layer covering the capping layer and covering the second source/drain regions.
9. The semiconductor device of claim 1 , further comprising:
gate spacer layers on opposite sides of the gate electrodes,
wherein, in the plan view at a level of an uppermost surface of the plurality of channel layers, the first source/drain regions and the second source/drain regions cover end portions of the gate spacer layers in the second direction.
10. The semiconductor device of claim 9 , wherein, in the plan view at the level of the uppermost surface of the plurality of channel layers, the end portions of the gate spacer layers protrude into the first source/drain regions and the second source/drain regions.
11. The semiconductor device of claim 1 , wherein the first source/drain regions comprise a first material and the second source/drain regions comprise a second material different from the first material.
12. The semiconductor device of claim 11 , wherein the first source/drain regions comprise silicon germanium (SiGe).
13. A semiconductor device comprising:
a substrate comprising a first active region and a second active region extending in a first direction, spaced apart from each other in a second direction, the first active region comprising impurities of a first conductivity type and the second active region comprising impurities of a second conductivity type different from the first conductivity type;
at least one gate electrode intersecting the first active region and the second active region and extending in the second direction;
a plurality of channel layers spaced apart from each other in a third direction on the first active region and the second active region and encompassed by the at least one gate electrode, the third direction being perpendicular to an upper surface of the substrate;
first source/drain regions on opposite sides of the at least one gate electrode on the first active region, the first source/drain regions being connected to the plurality of channel layers; and
second source/drain regions disposed on opposite sides of the at least one gate electrode on the second active region, the second source/drain regions being connected to the plurality of channel layers,
wherein the first source/drain regions and the second source/drain regions have different shapes in a plan view,
wherein an end portion of each of the first source/drain regions in the second direction in the plan view comprises a tip region protruding in the second direction, and
wherein each tip region comprises a triangular region in the plan view that points in the second direction.
14. The semiconductor device of claim 13 , wherein the end portion of each of the second source/drain regions in the second direction in the plan view is formed without a region protruding in the second direction.
15. The semiconductor device of claim 14 , wherein the end portion of each of the second source/drain regions in the second direction in the plan view has a substantially flat shape.
16. The semiconductor device of claim 13 , wherein the tip regions overlap the at least one gate electrode in the first direction, and
wherein the tip regions are formed without overlapping the plurality of channel layers in the first direction.
17. The semiconductor device of claim 13 , wherein each of the first source/drain regions has a maximum length in the second direction in a center of the first source/drain regions in the first direction.
18. A semiconductor device comprising:
a substrate comprising a first region, a second region, and active regions extending in a first direction in the first region and in the second region;
gate structures on the first region and the second region, the gate structures intersecting the active regions and extending in a second direction; and
first source/drain regions and second source/drain regions in respective portions of the active regions that are recessed on opposite sides of the gate structures,
wherein the first source/drain regions are in the first region and an end portion of each of the first source/drain regions in the second direction comprises a tip region protruding in the second direction in a plan view,
wherein the second source/drain regions are in the second region and an end portion of each of the second source/drain regions in the second direction is formed without a region protruding in the second direction in the plan view,
wherein a first length of a portion of each of the first source/drain regions in contact with at least one of the gate structures and extending in the second direction is greater than a second length by which each tip region protrudes in the second direction, and
wherein each tip region comprises a triangular region in the plan view that points in the second direction.
19. The semiconductor device of claim 18 , wherein the first length is equal to or greater than twice the second length.