Metal gate structure and method of forming the same
A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.
1. A method of manufacturing a semiconductor device, comprising:
forming a gate trench over a semiconductor substrate;
depositing a gate dielectric layer and a work function layer in the gate trench;
depositing a capping layer over the work function layer;
passivating a surface portion of the capping layer to form a passivation layer;
removing the passivation layer, wherein the removing of the passivation layer forms a metal-containing film on the capping layer;
depositing a fill layer in the gate trench;
recessing the fill layer and the capping layer; and
forming a contact metal layer above the capping layer in the gate trench.
2. The method of claim 1 , wherein the passivating of the surface portion of the capping layer includes an oxidation process and the passivation layer is an oxide.
3. The method of claim 2 , wherein the oxidation process is an oxygen plasma process.
4. The method of claim 1 , wherein the passivating of the surface portion of the capping layer includes a nitridation process and the passivation layer is a nitride.
5. The method of claim 1 , wherein the passivating of the surface portion of the capping layer includes applying a passivating species that has a higher concentration at an opening of the gate trench than at a bottom portion of the gate trench.
6. The method of claim 1 , wherein the passivation layer has a larger thickness near an opening of the gate trench than near a bottom portion of the gate trench.
7. The method of claim 1 , wherein after the removing of the passivation layer, an opening of the gate trench is enlarged.
8. The method of claim 1 , wherein the metal-containing film includes a metal element that is not included in the capping layer and the fill layer.
9. The method of claim 1 , wherein the recessing of the fill layer and the capping layer fully removes the fill layer from the gate trench.
10. The method of claim 1 , wherein the metal-containing film contains tungsten.
11. A method of manufacturing a semiconductor device, comprising:
forming a gate trench in a dielectric material by removing a dummy gate and by removing an upper portion of a gate spacer disposed on sidewalls of the dummy gate;
depositing a gate dielectric layer and a work function layer in the gate trench;
depositing a capping layer in the gate trench;
performing a passivation treatment to the capping layer to convert a surface portion of the capping layer to a passivation layer, wherein the passivation layer includes a larger thickness close to an opening of the gate trench than close to a bottom portion of the gate trench;
etching the passivation layer, thereby enlarging the opening of the gate trench; and
depositing a trench-filling layer in the gate trench.
12. The method of claim 11 , wherein the trench-filling layer fully fills the gate trench without trapping seams in the gate trench.
13. The method of claim 11 , further comprising:
recessing the trench-filling layer, the capping layer, the work function layer, and the gate dielectric layer; and
forming a contact metal layer directly above the capping layer and the work function layer in the gate trench.
14. The method of claim 13 , wherein the recessing fully removes the trench-filling layer from the gate trench.
15. The method of claim 11 , wherein prior to the depositing of the gate dielectric layer and the work function layer, the gate trench includes a lower trench and an upper trench above the lower trench, the upper trench is wider than the lower trench.
16. The method of claim 15 , wherein prior to the depositing of the gate dielectric layer and the work function layer, the opening of the gate trench is smaller than a middle portion of the upper trench, and wherein after the etching of the passivation layer, the opening of the gate trench is larger than the middle portion of the upper trench.
17. The method of claim 11 , wherein the capping layer contains a metal element.
18. A method, comprising:
forming a dummy gate structure;
depositing a first gate spacer on sidewalls of the dummy gate structure;
depositing a second gate spacer on sidewalls of the first gate spacer, wherein the first and second gate spacers include different material compositions;
removing the dummy gate structure and a top portion of the first gate spacer to form a gate trench, wherein the gate trench exposes a top portion of the second gate spacer;
depositing a gate dielectric layer and a work function layer in the gate trench;
depositing a capping layer over the work function layer;
passivating a surface portion of the capping layer to form a passivation layer, wherein the passivation layer has a larger thickness near an opening of the gate trench than near a bottom portion of the gate trench;
removing the passivation layer;
recessing the gate dielectric layer, the work function layer, and the capping layer to expose the second gate spacer in the gate trench; and
forming a gate contact in electrical coupling with the recessed capping layer and the work function layer.
19. The method of claim 18 , further comprising:
after the removing of the passivation layer, depositing a gap-filling layer in the gate trench.
20. The method of claim 19 , wherein a bottommost potion of the gap-filling layer is above a topmost portion of the first gate spacer.