Semiconductor devices, systems, and methods for forming the same
In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a second trench isolation in the substrate and surrounding a portion of the substrate, and a first routing electrode layer extending through the first trench isolation. The portion of the substrate is an active region of a transistor.
1. A semiconductor device, comprising:
a substrate;
a first trench isolation in the substrate;
a second trench isolation in the substrate and surrounding a portion of the substrate, wherein the portion of the substrate is an active region of a three-dimensional (3D) transistor, wherein the 3D transistor comprises a 3D semiconductor body extending through the second trench isolation; and
a first routing electrode layer extending through the first trench isolation.
2. The semiconductor device of claim 1 , further comprising:
a third trench isolation on the substrate; and
a second routing electrode layer on the third trench isolation.
3. The semiconductor device of claim 1 , further comprising:
a non-active region on the substrate; and
a third routing electrode layer on the non-active region.
4. The semiconductor device of claim 1 , further comprising:
an interconnect layer coupled to the first routing electrode layer.
5. The semiconductor device of claim 4 , further comprising:
a first peripheral circuit comprising the 3D transistor; and
a second peripheral circuit, wherein the first peripheral circuit is coupled to the second peripheral circuit through the interconnect layer.
6. The semiconductor device of claim 5 , wherein the second peripheral circuit comprises a planar transistor or a second 3D transistor.
7. The semiconductor device of claim 6 , wherein the 3D transistor further comprises:
a gate structure in contact with a side of the 3D semiconductor body, wherein the gate structure comprises a gate dielectric and a gate electrode.
8. The semiconductor device of claim 7 , wherein the 3D semiconductor body comprises:
the portion of the substrate;
a source; and
a drain, wherein the portion of the substrate is formed between the source and the drain.
9. The semiconductor device of claim 6 , wherein the planar transistor comprises:
a source;
a drain;
a channel surrounded by the source and the drain; and
a gate structure comprising a gate dielectric and a gate electrode.
10. The semiconductor device of claim 5 , further comprising:
an array of 3D NAND memory strings; and
a bonding layer, wherein the array of 3D NAND memory strings is coupled to the first peripheral circuit or the second peripheral circuit through the bonding layer and the interconnect layer.
11. A semiconductor device, comprising:
a semiconductor layer;
a first trench isolation at least partially embedded in the semiconductor layer;
a first routing electrode layer at least partially embedded in the first trench isolation;
a second trench isolation at least partially embedded in the semiconductor layer; and
a three-dimensional (3D) transistor comprising a 3D semiconductor body extending through the second trench isolation, wherein the 3D semiconductor body is a first portion of the semiconductor layer laterally surrounded by the second trench isolation and has a first top surface higher than a second top surface of a second portion of the semiconductor layer outside of the second trench isolation.
12. The semiconductor device of claim 11 , further comprising:
a third trench isolation at least partially embedded in the semiconductor layer; and
a second routing electrode layer on the third trench isolation.
13. The semiconductor device of claim 12 , wherein
the first portion of the semiconductor layer comprises an active region of the 3D transistor; and
the second portion of the semiconductor layer comprises a non-active region on which a third routing electrode layer is located.
14. The semiconductor device of claim 13 , further comprising:
an interconnect layer coupled to the first routing electrode layer, the second routing electrode layer, and the third routing electrode layer.
15. The semiconductor device of claim 14 , further comprising:
a first peripheral circuit comprising the 3D transistor; and
a second peripheral circuit, wherein the first peripheral circuit is coupled to the second peripheral circuit through the interconnect layer.
16. The semiconductor device of claim 15 , wherein the second peripheral circuit comprises a planar transistor or a second 3D transistor.
17. The semiconductor device of claim 16 , wherein the 3D transistor further comprises:
a gate structure in contact with a side of the 3D semiconductor body, wherein the gate structure comprises a gate dielectric and a gate electrode.
18. The semiconductor device of claim 17 , wherein the 3D semiconductor body comprises:
the active region;
a source on a first side of the active region; and
a drain on a second side of the active region opposite to the first side.
19. The semiconductor device of claim 16 , wherein the planar transistor comprises:
a source;
a drain;
a channel surrounded by the source and the drain; and
a gate structure comprising a gate dielectric and a gate electrode.
20. The semiconductor device of claim 15 , further comprising:
an array of 3D NAND memory strings; and
a bonding layer, wherein the array of 3D NAND memory strings is coupled to the first peripheral circuit or the second peripheral circuit through the bonding layer and the interconnect layer.