IP Library › Granted Patent US 12,432,951
Granted Patent B2
US 12,432,951 · App. 18/179,739 · Granted Sep 30, 2025

Semiconductor device and method of manufacturing the same

Inventors: Seigo Namioka (Tokyo, JP); Hitoshi Matsuura (Tokyo, JP); Ryota Kuroda (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H10D12/481H10D12/035H10D12/038H10D62/127H10D62/393H10D64/231
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Quick Facts
Patent No.
US 12,432,951
App. No.
18/179,739
Granted
Sep 30, 2025
Kind
B2
Abstract

A semiconductor device includes a trench emitter electrode located at a boundary between one end of an active cell region and an inactive cell region, a trench gate electrode located at a boundary between the other end of the active cell region and the inactive cell region, an end trench gate electrode connected to one end of the trench gate electrode, and an end trench emitter electrode connected to one end of the trench emitter electrode. A hole barrier region of a first conductivity type is provided under a body region of a second conductivity type between the end trench gate electrode and the end trench emitter electrode in a plan view. A body region in the active cell region and a body region in the inactive cell region are connected to each other by a body region between the end trench gate electrode and the end trench emitter electrode.

Claims (59)

1. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;

a drift region of a first conductivity type formed in the semiconductor substrate; and

a cell region formed on the first main surface of the semiconductor substrate,

the cell region includes:

an active cell region provided in the semiconductor substrate from the first main surface toward the drift region,

a trench gate electrode and a trench emitter electrode formed in a pair of trenches which is formed on a surface of the first main surface so as to extend in a first direction and sandwich the active cell region in a plan view,

a body region of a second conductivity type opposite to the first conductivity type formed in a surface region of the drift region at a side of the first main surface,

an inactive cell region provided in the semiconductor substrate at both sides of the active cell region so as to sandwich the active cell region and adjacent the trench gate electrode and the trench emitter electrode in a plan view,

an emitter region of the first conductivity type provided in the active cell region and formed in a surface region of the body region at the side of the first main surface;

a contact hole in contact with the trench emitter electrode, the emitter region and the body region;

a first hole barrier region of the first conductivity type which is formed in the drift region under the body region in the active cell region and has an impurity concentration higher than that of the drift region and lower than that of the emitter region;

a floating region of the second conductivity type formed under the body region in the inactive cell region;

an end trench gate electrode connected to one end of the trench gate electrode and extending in a second direction different from the first direction in a plan view and formed in the surface of the first main surface; and

an end trench emitter electrode connected to one end of the trench emitter electrode and extending in the second direction in a plan view and formed in the surface region on the first main surface in the inactive cell region,

wherein a second hole barrier region of the first conductivity type formed in the drift region under the body region between the end trench gate electrode and the end trench emitter electrode in a plan view and having an impurity concentration higher than that of the drift region and lower than that of the emitter region, and

wherein the body region in the active cell region and the body region in the inactive cell region are connected by the body region between the end trench gate electrode and the end trench emitter electrode.

2. A semiconductor device according to claim 1 , further comprising a second end trench emitter electrode and a third end trench emitter electrode in a trench provided in the surface region on the first main surface in the inactive cell region,

wherein the other end of the end trench emitter electrode is connected to one end of the third end trench emitter electrode,

wherein the third end trench emitter electrode extends in the first direction in a plan view and the other end of the third end trench emitter electrode is connected to one end of the second end trench emitter electrode,

wherein the second end trench emitter electrode extends in the second direction in a plan view and the other end of the second end trench emitter electrode is connected to the trench emitter electrode.

3. A semiconductor device according to claim 2 , further comprising a second trench gate electrode in a trench adjacent to the inactive cell region and provided in the surface region of the first main surface and extending in the first direction in a plan view,

wherein the second hole barrier region is extended at a lower portion of the body region and an upper portion of the drift region in a region between the second trench gate electrode and the third end trench emitter electrode, and

wherein the floating region is extended at the lower portion of the body region and the upper portion of the drift region and is adjacent to the second hole barrier region.

4. A semiconductor device according to claim 1 , wherein the second hole barrier region is spaced apart from the first hole barrier region by the drift region.

5. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;

a drift region of a first conductivity type formed in the semiconductor substrate; and

a cell region formed on the first main surface of the semiconductor substrate,

the cell region includes:

an active cell region provided in the semiconductor substrate from the first main surface toward the drift region,

a trench gate electrode and a trench emitter electrode formed in a pair of trenches which is formed on a surface of the first main surface so as to extend in a first direction and sandwich the active cell region in a plan view,

a body region of a second conductivity type opposite to the first conductivity type formed in a surface region of the drift region at a side of the first main surface,

an inactive cell region provided in the semiconductor substrate at both sides of the active cell region so as to sandwich the active cell region and adjacent the trench gate electrode and the trench emitter electrode in a plan view,

an emitter region of the first conductivity type provided in the active cell region and formed in a surface region of the body region at the side of the first main surface;

a contact hole in contact with the trench emitter electrode, the emitter region and the body region;

a first hole barrier region of the first conductivity type which is formed in the drift region under the body region in the active cell region and has an impurity concentration higher than that of the drift region and lower than that of the emitter region;

a floating region of the second conductivity type formed under the body region in the inactive cell region;

an end trench gate electrode connected to one end of the trench gate electrode and extending in a second direction different from the first direction in a plan view and formed in the surface of the first main surface; and

an end trench emitter electrode connected to one end of the trench emitter electrode and extending in the second direction in a plan view and formed in the surface region on the first main surface in the inactive cell region,

wherein an isolation region of the first conductivity type for separating the body region and the floating region is provided between the end trench gate electrode and the end trench emitter electrode in a plan view, and

wherein a semiconductor region of the second conductivity type is further provided in a surface region of the isolation region so as to connect the body region and the floating region.

6. A semiconductor device according to claim 5 , wherein the semiconductor region of the second conductivity type is formed of a semiconductor layer that is the same layer as the body region.

7. A semiconductor device according to claim 6 , wherein the isolation region of the first conductivity type is formed of a semiconductor layer that is the same layer as the first hole barrier region of the first conductivity type.

8. A method of manufacturing a semiconductor device having:

a trench emitter electrode extending in a first direction in a plan view and located at a boundary between one end of an active cell region and a first inactive cell region;

a trench gate electrode extending in the first direction in a plan view and located at a boundary between the other end of the active cell region and a second inactive cell region;

an end trench gate electrode connected to one end of the trench gate electrode and extending in a second direction different from the first direction in a plan view; and

an end trench emitter electrode connected to one end of the trench emitter electrode in the first inactive cell region and extending in the second direction in a plan view,

the method comprising the steps of:

defining a first region and a second region adjacent to each other in a semiconductor substrate of a first conductivity type having a first surface;

forming the trench gate electrode and the end trench gate electrode in a first trench reaching a first depth from the first surface of the semiconductor substrate in the first region, via a first insulating film;

forming the trench emitter electrode and the end trench emitter electrode in a second trench reaching the first depth from the first surface of the semiconductor substrate in the first region, via a second insulating film, the second trench is spaced apart from the first trench;

forming a hole barrier region by introducing an impurity of a first conductivity type into the semiconductor substrate located in the first region;

forming a floating region by introducing an impurity of a second conductivity type into the semiconductor substrate located in the second region;

forming a first semiconductor region of the first conductivity type from the first surface to a second depth of the semiconductor substrate located in the first region between the trench gate electrode and the trench emitter electrode;

forming a second semiconductor region of the second conductivity type in the semiconductor substrate that is positioned in the first region between the trench gate electrode and the trench emitter electrode and in the second region between the end trench gate electrode and the end trench emitter electrode such that the second semiconductor region being deeper than the second depth and shallower than the first depth;

forming an opening in the trench emitter electrode, the first semiconductor region and the second semiconductor region; and

forming a contact portion electrically connected to the trench emitter electrode, the first semiconductor region and the second semiconductor region in the opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2023
From: NAMIOKA, SEIGO; MATSUURA, HITOSHI; KURODA, RYOTA
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 062949/0904 →
Priority Claims (1)
JP 2022-103090 · Jun 28, 2022 · national
Continuity (1)
Related Publication 20230420550A1 · Dec 28, 2023
References Cited (4)
US 10505029B2 · Nagata · 2019 [cited by applicant]
US 20170278956A1 · Tsuyuki · 2017 [cited by examiner]
US 20200212209A1 · Nagata · 2020 [cited by examiner]
JP 2019029434A · 2019 [cited by applicant]