Peak power management data burst communication
A memory device includes memory dies. Each memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication. The operations include monitoring a data burst with respect to the memory array, detecting a current reservation trigger associated with the data burst, in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst, detecting a plurality of input/output cycles of the data burst following the preamble period, and in response to detecting the number of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.
1. A memory device comprising:
a plurality of memory dies, each memory die of the plurality of memory dies comprising;
a memory array; and
control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication, the operations comprising:
monitoring a data burst with respect to the memory array;
detecting a current reservation trigger associated with the data burst;
in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst;
detecting a plurality of input/output cycles of the data burst following a preamble period of the data burst; and
in response to detecting the plurality of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.
2. The memory device of claim 1 , wherein the operations further comprise:
detecting a postamble period of the data burst following the plurality of input/output cycles, wherein the postamble period corresponds to an idle timing mode of the data burst; and
in response to detecting the postamble period, reserving a final amount of current reflecting an idle current consumption value associated with the data burst.
3. The memory device of claim 1 , wherein the maximum current consumption value corresponds to a maximum timing mode of the data burst, and wherein the actual current consumption value corresponds to an actual timing mode of the data burst determined from the analysis of the plurality of input/output cycles.
4. The memory device of claim 1 , wherein:
reserving the initial amount of current comprises communicating the initial amount of current to other memory dies of the plurality of memory dies via a token ring protocol; and
reserving the subsequent amount of current comprises communicating the subsequent amount of current to the other memory dies via the token ring protocol.
5. The memory device of claim 1 , wherein reserving the subsequent amount of current comprises converting, using a current consumption data structure, an actual timing mode value defining an actual timing mode of the data burst into the actual current consumption value.
6. The memory device of claim 5 , wherein the actual timing mode value corresponds to a multiplier of a base current consumption value, and wherein converting the actual timing mode value into the actual current consumption value comprises determining the actual current consumption value by multiplying the base current consumption value by the multiplier.
7. The memory device of claim 1 , wherein detecting the current reservation trigger comprises detecting at least one of: the preamble period of the data burst, or a data input/output start command.
8. A method comprising:
monitoring, by a processing device, a data burst with respect to a memory array of a memory die of a peak power management (PPM) network;
detecting, by the processing device, a current reservation trigger associated with the data burst;
in response detecting the current reservation trigger, reserving, by the processing device, an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst;
detecting, by the processing device, a plurality of input/output cycles of the data burst following a preamble period of the data burst; and
in response to detecting the plurality of input/output cycles, reserving, by the processing device based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.
9. The method of claim 8 , further comprising:
detecting, by the processing device, a postamble period of the data burst following the plurality of input/output cycles, wherein the postamble period corresponds to an idle timing mode of the data burst; and
in response to detecting the postamble period, reserving, by the processing device, a final amount of current reflecting an idle current consumption value associated with the data burst.
10. The method of claim 8 , wherein the maximum current consumption value corresponds to a maximum timing mode of the data burst, and wherein the actual current consumption value corresponds to an actual timing mode of the data burst determined from the analysis of the plurality of input/output cycles.
11. The method of claim 8 , wherein:
reserving the initial amount of current comprises communicating the initial amount of current to other memory dies of the PPM network via a token ring protocol; and
reserving the subsequent amount of current comprises communicating the subsequent amount of current to the other memory dies of the PPM network via the token ring protocol.
12. The method of claim 8 , wherein reserving the subsequent amount of current comprises converting, using a current consumption data structure, an actual timing mode value defining an actual timing mode of the data burst into the actual current consumption value.
13. The method of claim 12 , wherein the actual timing mode value corresponds to a multiplier of a base current consumption value, and wherein converting the actual timing mode value into the actual current consumption value comprises determining the actual current consumption value by multiplying the base current consumption value by the multiplier.
14. The method of claim 8 , wherein detecting the current reservation trigger comprises detecting at least one of: the preamble period of the data burst, or a data input/output start command.
15. A memory device comprising:
a plurality of memory dies, each memory die of the plurality of memory dies comprising;
a memory array; and
control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication, the operations comprising:
receiving a timing mode value defining a timing mode associated with a data transfer speed of a data burst with respect to the memory array;
converting, by using a base current consumption value, the timing mode value into a current consumption value; and
reserving an amount of current for the data burst based on the current consumption value.
16. The memory device of claim 15 , wherein reserving the amount of current comprises communicating the amount of current to other memory dies of the plurality of memory dies via a token ring protocol.
17. The memory device of claim 15 , wherein the timing mode value is a maximum timing mode value defining a maximum timing mode associated with a maximum data transfer speed of the data burst, wherein the current consumption value is a maximum current consumption value, and wherein the amount of current reflects the maximum current consumption value.
18. The memory device of claim 15 , wherein the timing mode value is an actual timing mode value defining an actual timing mode associated with an actual data transfer speed of the data burst, wherein the current consumption value is an actual current consumption value, and wherein the amount of current reflects the actual current consumption value.
19. The memory device of claim 15 , wherein:
the timing mode value corresponds to a multiplier of a base current consumption value; and
converting the timing mode value into the current consumption value by using the base current consumption value comprises converting, using a current consumption data structure, the timing mode value into the current consumption value by multiplying the base current consumption value by the multiplier.
20. The memory device of claim 15 , wherein the timing mode value is an idle timing mode value defining an idle timing mode associated with an idle data transfer speed of the data burst, wherein the current consumption value is an idle current consumption value, and wherein the amount of current reflects the idle current consumption value.