IP Library › Granted Patent US 12,439,599
Granted Patent B2
US 12,439,599 · App. 17/931,923 · Granted Oct 7, 2025

Semiconductor memory device

Inventors: Hikari Tajima (Tokyo, JP); Masayuki Kitamura (Yokkaichi Mie, JP); Seiichi Omoto (Yokkaichi Mie, JP)
Assignee: Kioxia Corporation
H10B43/27H10B43/10H10B43/35
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Quick Facts
Patent No.
US 12,439,599
App. No.
17/931,923
Granted
Oct 7, 2025
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of conductive layers containing molybdenum (Mo) are stacked to be spaced apart from each other in a first direction, a pillar structure including a semiconductor layer extending in the first direction in the stacked body, a partition structure extending in the first direction and in a second direction intersecting the first direction in the stacked body, and dividing the stacked body in a third direction intersecting the first and second directions, and a plurality of intermediate layers, each including a portion provided between the pillar structure and a corresponding one of the conductive layers, and containing a compound of molybdenum (Mo) and boron (B).

Claims (48)

1. A semiconductor memory device comprising:

a stacked body in which a plurality of conductive layers containing molybdenum (Mo) are stacked to be spaced apart from each other in a first direction;

a pillar structure including a semiconductor layer extending in the first direction in the stacked body;

a partition structure extending in the first direction and in a second direction intersecting the first direction in the stacked body, and dividing the stacked body in a third direction intersecting the first and second directions; and

a plurality of intermediate layers, each including a portion provided between the pillar structure and a corresponding one of the conductive layers, and containing a compound of molybdenum (Mo) and boron (B).

2. The device of claim 1 , wherein

each of the plurality of intermediate layers further includes portions provided along a lower surface and an upper surface of the corresponding one of the conductive layers.

3. The device of claim 2 , wherein

each of the plurality of intermediate layers further includes a portion provided between the partition structure and the corresponding one of the conductive layers.

4. The device of claim 2 , wherein

each of the plurality of intermediate layers does not include a portion provided between the partition structure and the corresponding one of the conductive layers.

5. The device of claim 4 , wherein

positions of side surfaces of the portions provided along the lower surface and the upper surface of the corresponding one of the conductive layers are recessed on a side of the pillar structure relative to a position of a side surface of the corresponding one of the conductive layers.

6. The device of claim 1 , wherein

each of the plurality of intermediate layers further includes a portion provided between the partition structure and the corresponding one of the conductive layers.

7. The device of claim 1 , wherein

a composition ratio of molybdenum (Mo) and boron (B) contained in each of the plurality of intermediate layers is approximately 1:1.

8. The device of claim 1 , further comprising:

a plurality of first block insulating layers each including a portion provided between the pillar structure and the corresponding one of the conductive layers,

wherein

each of the plurality of intermediate layers is provided between the corresponding one of the conductive layers and a corresponding one of the first block insulating layers.

9. The device of claim 8 , wherein

each of the plurality of first block insulating layers contains at least one of a compound of aluminum (Al) and oxygen (O), a compound of zirconium (Zr) and oxygen (O), or a compound of hafnium (Hf) and oxygen (O).

10. The device of claim 1 , wherein

the pillar structure further includes a charge storage layer surrounding a side surface of the semiconductor layer.

11. The device of claim 10 , wherein

the pillar structure further includes a second block insulating layer surrounding a side surface of the charge storage layer and containing silicon oxide.

12. The device of claim 1 , wherein

the partition structure includes a conductive portion.

13. The device of claim 1 , wherein

the stacked body includes a structure in which the plurality of conductive layers and a plurality of insulating layers are stacked alternately in the first direction.

14. A semiconductor memory device comprising:

a stacked body in which a plurality of conductive layers containing molybdenum (Mo) are stacked to be spaced apart from each other in a first direction;

a pillar structure including a semiconductor layer extending in the first direction in the stacked body;

a partition structure extending in the first direction and in a second direction intersecting the first direction in the stacked body, and dividing the stacked body in a third direction intersecting the first and second directions; and

a plurality of intermediate layers, each including a portion provided between the partition structure and a corresponding one of the conductive layers, and containing a compound of molybdenum (Mo) and boron (B).

15. The device of claim 14 , wherein

each of the plurality of intermediate layers further includes portions provided along a lower surface and an upper surface of the corresponding one of the conductive layers.

16. The device of claim 14 , wherein

a composition ratio of molybdenum (Mo) and boron (B) contained in each of the plurality of intermediate layers is approximately 1:1.

17. The device of claim 14 , wherein

the pillar structure further includes a charge storage layer surrounding a side surface of the semiconductor layer.

18. The device of claim 17 , wherein

the pillar structure further includes a block insulating layer surrounding a side surface of the charge storage layer and containing silicon oxide.

19. The device of claim 14 , wherein

the partition structure includes a conductive portion.

20. The device of claim 14 , wherein

the stacked body includes a structure in which the plurality of conductive layers and a plurality of insulating layers are stacked alternately in the first direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2022
From: TAJIMA, HIKARI; KITAMURA, MASAYUKI; OMOTO, SEIICHI
To: KIOXIA CORPORATION
Reel/Frame 062041/0835 →
Priority Claims (1)
JP 2022-015650 · Feb 3, 2022 · national
Continuity (1)
Related Publication 20230247833A1 · Aug 3, 2023
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