Semiconductor power device and method of manufacturing the same
The application relates to a semiconductor power device including a semiconductor body in which a transistor device is formed, the transistor device having a gate region and a channel region laterally aside the gate region, the gate region including a gate electrode for controlling a channel formation in the channel region, and a gate dielectric laterally between the channel region and the gate electrode. The gate electrode includes a gate electrode bulk region and a gate electrode layer laterally between the gate dielectric and the gate electrode bulk region. The gate electrode layer is made of a doped metallically conductive material.
1. A semiconductor power device, comprising:
a semiconductor body in which a transistor device is formed;
a source region of the transistor device at a frontside of the semiconductor body;
a drain region of the transistor device at a backside of the semiconductor body;
a gate region of the transistor device; and
a channel region of the transistor device laterally aside the gate region and vertically between the source region and the drain region,
wherein in an upper part of the gate region that laterally adjoins both the source region and the channel region, the gate region comprises a gate electrode for controlling a channel formation in the channel region, and a gate dielectric laterally between the channel region and the gate electrode,
wherein the gate electrode comprises a gate electrode bulk region and a gate electrode layer laterally between the gate dielectric and the gate electrode bulk region,
wherein the gate electrode layer comprises titanium nitride, titanium, titanium tungsten, tungsten, or cobalt,
wherein the gate electrode layer is doped with at least one doping agent selected from the group consisting of: fluorine; nitrogen; carbon; aluminum; oxygen; and hydrogen,
wherein the gate electrode bulk region comprises doped polysilicon.
2. The semiconductor power device of claim 1 , wherein the gate electrode layer extends vertically between a lower end and an upper end, and wherein the upper end of the gate electrode layer is arranged recessed with respect to a frontside of the semiconductor body.
3. The semiconductor power device of claim 1 , further comprising a MOS-gated diode (MGD) formed in the semiconductor body, wherein an MGD gate region of the MOS-gated diode comprises an MGD interlayer dielectric and an MGD gate electrode, the MGD gate electrode having an MGD gate electrode bulk region formed directly adjacent the MGD interlayer dielectric.
4. The semiconductor power device of claim 3 , wherein the gate electrode bulk region of the transistor device and the MGD gate electrode bulk region are made of a same material.
5. The semiconductor power device of claim 1 , further comprising an additional transistor device formed in the semiconductor body and which comprises a gate region with a gate electrode and a gate dielectric, the gate electrode of the additional transistor device having a gate electrode bulk region and a gate electrode layer laterally between the gate dielectric and the gate electrode bulk region, and wherein the gate electrode layer of the additional transistor device has different material properties than the gate electrode layer of the transistor device.
6. The semiconductor power device of claim 1 , further comprising an additional transistor device formed in the semiconductor body and which comprises a gate region with a gate electrode and a gate dielectric, wherein the gate electrode of the additional transistor device has a gate electrode bulk region formed directly adjacent the gate dielectric.
7. An arrangement, comprising:
a plurality semiconductor power devices each of which comprises a semiconductor body in which a transistor device is formed, the transistor device having a source region at a frontside of the semiconductor body, a drain region at a backside of the semiconductor body, a gate region, and a channel region laterally aside the gate region and vertically between the source region and the drain region, wherein in an upper part of the gate region that laterally adjoins both the source region and the channel region, the gate region comprises a gate electrode for controlling a channel formation in the channel region, and a gate dielectric laterally between the channel region and the gate electrode, the gate electrode comprising a gate electrode bulk region and a gate electrode layer laterally between the gate dielectric and the gate electrode bulk region, the gate electrode layer comprising titanium nitride, titanium, titanium tungsten, tungsten, or cobalt,
wherein the gate electrode bulk region of the plurality semiconductor power devices comprises doped polysilicon,
wherein the gate electrode layer of the plurality semiconductor power devices is doped with at least one doping agent selected from the group consisting of: fluorine; nitrogen; carbon; aluminum; oxygen; and hydrogen.
8. A method for manufacturing a semiconductor power device, the method comprising:
forming a source region of a transistor device in at a frontside of a semiconductor body;
forming a drain region of the transistor device at a backside of the semiconductor body;
forming a gate region of the transistor device; and
forming a channel region of the transistor device laterally aside the gate region and vertically between the source region and the drain region,
wherein forming the gate region comprises forming, in an upper part of the gate region that laterally adjoins both the source region and the channel region, a gate electrode for controlling a channel formation in the channel region and a gate dielectric laterally between the channel region and the gate electrode,
wherein forming the gate electrode comprises forming a gate electrode bulk region and a gate electrode layer laterally between the gate dielectric and the gate electrode bulk region, the gate electrode bulk region comprising doped polysilicon and the gate electrode layer comprising titanium nitride, titanium, titanium tungsten, tungsten, or cobalt,
wherein forming the gate electrode layer comprises doping the gate electrode layer with at least one doping agent selected from the group consisting of: fluorine; nitrogen; carbon; aluminum; oxygen; and hydrogen.
9. The method of claim 8 , further comprising:
forming a MOS-gated diode (MGD) in the semiconductor body, wherein an MGD gate region of the MOS-gated diode comprises an MGD interlayer dielectric and an MGD gate electrode, the MGD gate electrode having an MGD gate electrode bulk region formed directly adjacent the MGD interlayer dielectric.
10. The method of claim 9 , wherein a sidewall of the MGD interlayer dielectric, which lies laterally opposite to an MGD channel region of the MOS-gated diode, is covered when the gate electrode layer of the transistor device is being formed.
11. The method of claim 9 , wherein when the gate electrode layer of the transistor device is being formed, the MGD interlayer dielectric is covered by the MGD gate electrode.
12. The method of claim 9 , wherein when the titanium nitride, titanium, titanium tungsten, tungsten, or cobalt is deposited for forming the gate electrode layer of the transistor device, a layer of the titanium nitride, titanium, titanium tungsten, tungsten, or cobalt is simultaneously formed, covering the MGD gate electrode, and wherein the layer of the titanium nitride, titanium, titanium tungsten, tungsten, or cobalt protects the MGD gate electrode during a recess etch of the gate electrode bulk material.