Memory including ECC engine
A memory may include a memory core; a first ECC engine configured to correct an error having a first pattern, the error occurring in read data read from the memory core; and a second ECC engine configured to correct an error having a second pattern, the error occurring in the read data read from the memory core. One of the first ECC engine and the second ECC engine may be selectively activated based on an address used to access the memory core.
1. A memory comprising:
a memory core;
a first ECC engine configured to correct an error having a first pattern, occurring in read data read from the memory core;
a second ECC engine configured to correct an error having a second pattern, occurring in the read data read from the memory core, wherein one of the first ECC engine and the second ECC engine is selectively activated based on an address used to access the memory core; and
a data swap circuit configured to change an arrangement of data transmitted between a selected ECC engine and the memory core according to the address.
2. The memory of claim 1 , wherein:
during a write operation of the memory, the selected ECC engine is configured to generate a write error correction code by using write data, and the write data and the write error correction code are written to the memory core; and
during a read operation of the memory, the selected ECC engine is configured to correct the error in the read data by using the read data and a read error correction code.
3. The memory of claim 1 , wherein:
the first ECC engine is configured to correct a random 1-bit error in the read data and a 2-bit error arranged in the first pattern; and
the second ECC engine is configured to correct the random 1-bit error in the read data and a 2-bit error arranged in the second pattern.
4. The memory of claim 1 , wherein the data swap circuit is configured to further change an arrangement of an error correction code transmitted between the selected ECC engine and the memory core according to the address.
5. The memory of claim 1 , wherein:
the address includes a row address and a column address; and
the selected ECC engine is selected depending on whether a value of the row address is an even number or an odd number.
6. The memory of claim 5 , wherein:
when the second ECC engine is selected, the data swap circuit is configured to change the arrangement of the data depending on whether a value of the column address is an even number or an odd number; and
when the first ECC engine is selected, the data swap circuit is configured not to change the arrangement of the data.
7. The memory of claim 1 , wherein error patterns mainly occurring in data read from the memory core are different depending on the address.
8. A memory comprising:
a memory core;
an ECC engine configured to correct an error in data read from the memory core; and
a data swap circuit configured to change an arrangement of data transmitted between the ECC engine and the memory core based on an address used to access the memory core.
9. The memory of claim 8 , wherein:
during a write operation of the memory, the ECC engine is configured to generate a write error correction code by using write data, and the write data and the write error correction code are written to the memory core; and
during a read operation of the memory, the ECC engine is configured to correct an error in the read data by using the read data and a read error correction code.
10. The memory of claim 9 , wherein the data swap circuit is configured to further change an arrangement of an error correction code transmitted between the ECC engine and the memory core according to the address.
11. The memory of claim 8 , wherein:
the address includes a row address and a column address; and
the data swap circuit is configured to change the arrangement depending on whether a value of the row address is an even number or an odd number.
12. The memory of claim 8 , wherein:
the address includes a row address and a column address; and
the data swap circuit is configured to change the arrangement depending on whether a value of the column address is an even number or an odd number.
13. The memory of claim 8 , wherein error patterns mainly occurring in data read from the memory core are different depending on the address.
14. An operation method of a memory, the operation method comprising:
correcting, by a first ECC engine, an error having a first pattern, occurring in read data read from a memory core based on an address used to access the memory core;
correcting, by a second ECC engine, an error having a second pattern, occurring in the read data read from the memory core based on the address; and
changing, by a data swap circuit, an arrangement of data transmitted between the memory core and one of the first ECC engine and the second ECC engine based on the address.
15. The operation method of claim 14 , further comprising changing, by the data swap circuit an arrangement of an error correction code transmitted between the memory core and the one of the first ECC engine and the second ECC engine based on the address.