Granted Patent B2

US 12,444,340 · App. 18/602,092 · Granted Oct 14, 2025

Inventor: Yingteng Zhai (Xiamen, CN)

Assignee: Tianma Advanced Display Technology Institute (Xiamen) Co., Ltd.

G09G3/2081G09G3/2011G09G3/2014G09G3/32G09G3/3233G09G2300/0819G09G2310/062G09G2310/08G09G2320/0633G09G2320/064

Abstract

Claims (80)

1. A display panel, comprising pixel circuits and light-emitting elements, wherein

a pixel circuit among the pixel circuits comprises an amplitude modulation circuit and a pulse width modulation circuit;

the amplitude modulation circuit comprises an amplitude driving sub-module and an amplitude reset sub-module, wherein the amplitude reset sub-module is configured to transmit a first reset signal to a control terminal of the amplitude driving sub-module;

the pulse width modulation circuit comprises a pulse width driving sub-module and a pulse width reset sub-module, wherein the pulse width reset sub-module is configured to transmit a second reset signal to a control terminal of the pulse width driving sub-module; and

a voltage value of the first reset signal is Vref1, and a voltage value of the second reset signal is Vref2; wherein

the amplitude modulation circuit comprises an amplitude data write sub-module configured to transmit a first data signal to the amplitude driving sub-module;

the pulse width modulation circuit comprises a pulse width data write sub-module configured to transmit a second data signal to the pulse width driving sub-module; and

a voltage value of the first data signal is Vdata1, a voltage value of the second data signal is Vdata2; and wherein Vdata1<Vdata2, Vref1<Vref2;

wherein the amplitude reset sub-module is electrically connected to a first reset signal line, and the pulse width reset sub-module is electrically connected to a second reset signal line; and the first reset signal line is configured to transmit the first reset signal, and the second reset signal line is configured to transmit the second reset signal; and

wherein the amplitude modulation circuit comprises an amplitude data write sub-module connected to a first data line;

the pulse width modulation circuit comprises a pulse width data write sub-module connected to a second data line; and

a control terminal of the amplitude data write sub-module and a control terminal of the pulse width data write sub-module are electrically connected to a same second scanning line.

2. The display panel of claim 1 , wherein the amplitude reset sub-module and the pulse width reset sub-module are electrically connected to a same reset signal line, and the reset signal line is configured to transmit the first reset signal and the second reset signal in a time-sharing manner.

3. The display panel of claim 2 , wherein the amplitude modulation circuit comprises an amplitude data write sub-module configured to transmit the first data signal to the amplitude driving sub-module;

the pulse width modulation circuit comprises a pulse width data write sub-module configured to transmit the second data signal to the pulse width driving sub-module;

an operating process of the display panel comprises a first period and a second period in time of one frame of image, wherein the first period does not overlap the second period;

in the first period, the reset signal line is configured to transmit the first reset signal, and the amplitude data write sub-module is turned on; and

in the second period, the reset signal line is configured to transmit the second reset signal, and the pulse width data write sub-module is turned on.

4. The display panel of claim 3 , comprising multiple rows of pixel circuits, wherein

in the first period, amplitude reset sub-modules in the multiple rows of pixel circuits are turned on simultaneously, and amplitude data write sub-modules in the multiple rows of pixel circuits are turned on simultaneously; and

in the second period, pulse width reset sub-modules in the multiple rows of pixel circuits are turned on row by row, and pulse width data write sub-modules in the multiple rows of pixel circuits are turned on row by row.

5. The display panel of claim 4 , wherein the first period is before the second period; or

wherein a control terminal of the amplitude reset sub-module and a control terminal of the pulse width reset sub-module are connected to different scanning lines.

6. The display panel of claim 3 , wherein

the amplitude reset sub-module comprises a first reset transistor, a first electrode of the first reset transistor is electrically connected to the reset signal line, and a second electrode of the first reset transistor is electrically connected to the control terminal of the amplitude driving sub-module;

the pulse width reset sub-module comprises a second reset transistor, a first electrode of the second reset transistor is electrically connected to the reset signal line, and a second electrode of the second reset transistor is electrically connected to the control terminal of the pulse width driving sub-module;

in the case where Vref1<Vref2, a gate of the first reset transistor is electrically connected to the reset signal line, and a gate of the second reset transistor is electrically connected to a scanning line.

7. The display panel of claim 1 , wherein a control terminal of the amplitude reset sub-module and a control terminal of the pulse width reset sub-module are connected to a same first scanning line.

8. The display panel of claim 1 , wherein the pixel circuits comprise a first pixel circuit and a second pixel circuit, the light-emitting elements comprise a first light-emitting element and a second light-emitting element, the first pixel circuit is configured to drive the first light-emitting element, the second pixel circuit is configured to drive the second light-emitting element, and an emitted color of the first light-emitting element is different from an emitted color of the second light-emitting element;

a voltage value of the first reset signal transmitted by an amplitude reset sub-module in the first pixel circuit is Vref11, and a voltage value of the second reset signal transmitted by a pulse width driving sub-module in the first pixel circuit is Vref21; and

a voltage value of the first reset signal transmitted by an amplitude reset sub-module in the second pixel circuit is Vref12, and a voltage value of the second reset signal transmitted by a pulse width driving sub-module in the second pixel circuit is Vref22;

wherein Vref11≠Vref12, and/or Vref21≠Vref22.

9. The display panel of claim 1 , wherein

operating modes of the display panel comprise a first mode and a second mode, wherein brightness of the display panel in the first mode is different from brightness of the display panel in the second mode;

in the first mode, the voltage value of the first reset signal is Vref15, and the voltage value of the second reset signal is Vref25; and

in the second mode, the voltage value of the first reset signal is Vref16, and the voltage value of the second reset signal is Vref26;

wherein |Vref15−Vref25|≠|Vref16−Vref26|.

10. The display panel of claim 9 , wherein

the brightness of the display panel in the first mode is less than the brightness of the display panel in the second mode, wherein

| V ref15− V ref25|<| V ref16− V ref26|.

11. The display panel of claim 1 , wherein

the amplitude modulation circuit further comprises an anode reset sub-module configured to transmit a third reset signal to an anode of one of the light-emitting elements; and

a voltage value of the third reset signal is Vref3, wherein Vref3≠Vref2.

12. A display apparatus, comprising a display panel according to claim 1 .

13. A driving method of a display panel, wherein the display panel comprises pixel circuits and light-emitting elements;

a pixel circuit among the pixel circuits comprises an amplitude modulation circuit and a pulse width modulation circuit;

the amplitude modulation circuit comprises an amplitude driving sub-module and an amplitude reset sub-module, wherein the amplitude reset sub-module is configured to transmit a first reset signal to a control terminal of the amplitude driving sub-module;

the pulse width modulation circuit comprises a pulse width driving sub-module and a pulse width reset sub-module, wherein the pulse width reset sub-module is configured to transmit a second reset signal to a control terminal of the pulse width driving sub-module; and

wherein the amplitude reset sub-module is electrically connected to a first reset signal line, and the pulse width reset sub-module is electrically connected to a second reset signal line; and

the first reset signal line is configured to transmit the first reset signal, and the second reset signal line is configured to transmit the second reset signal; and

wherein the amplitude modulation circuit comprises an amplitude data write sub-module connected to a first data line;

the pulse width modulation circuit comprises a pulse width data write sub-module connected to a second data line; and

a control terminal of the amplitude data write sub-module and a control terminal of the pulse width data write sub-module are electrically connected to a same second scanning line; and

wherein the driving method comprises:

controlling a voltage value of the first reset signal to be Vref1, and controlling a voltage value of the second reset signal to be Vref2; and

the amplitude modulation circuit comprises an amplitude data write sub-module configured to transmit a first data signal to the amplitude driving sub-module;

the pulse width modulation circuit comprises a pulse width data write sub-module configured to transmit a second data signal to the pulse width driving sub-module; and

the driving method further comprises:

controlling a voltage value of the first data signal to be Vdata1, and controlling a voltage value of the second data signal to be Vdata2;

and wherein Vdata1<Vdata2, Vref1<Vref2.

14. A display panel, comprising pixel circuits and light-emitting elements, wherein

a pixel circuit among the pixel circuits comprises an amplitude modulation circuit and a pulse width modulation circuit;

the amplitude modulation circuit comprises an amplitude driving sub-module and an amplitude reset sub-module, wherein the amplitude reset sub-module is configured to transmit a first reset signal to a control terminal of the amplitude driving sub-module;

the pulse width modulation circuit comprises a pulse width driving sub-module and a pulse width reset sub-module, wherein the pulse width reset sub-module is configured to transmit a second reset signal to a control terminal of the pulse width driving sub-module; and

a voltage value of the first reset signal is Vref1, and a voltage value of the second reset signal is Vref2, wherein Vref1≠Vref2; and

wherein operating modes of the display panel comprise a first mode and a second mode, wherein brightness of the display panel in the first mode is different from brightness of the display panel in the second mode;

in the first mode, the voltage value of the first reset signal is Vref15, and the voltage value of the second reset signal is Vref25; and

in the second mode, the voltage value of the first reset signal is Vref16, and the voltage value of the second reset signal is Vref26;

wherein |Vref15−Vref25|+|Vref16−Vref26|.

15. The display panel of claim 14 , wherein

the brightness of the display panel in the first mode is less than the brightness of the display panel in the second mode, wherein

| V ref15− V ref25|<| V ref16− V ref26|.

16. The display panel of claim 14 , wherein Vref1<Vref2.

17. The display panel of claim 14 , wherein Vref1>Vref2.

18. The display panel of claim 14 , wherein

the amplitude modulation circuit comprises an amplitude data write sub-module configured to transmit a first data signal to the amplitude driving sub-module;

the pulse width modulation circuit comprises a pulse width data write sub-module configured to transmit a second data signal to the pulse width driving sub-module; and

a voltage value of the first data signal is Vdata1, and a voltage value of the second data signal is Vdata2, wherein Vdata1≠Vdata2.

19. The display panel of claim 18 , wherein Vdata1<Vdata2.

20. The display panel of claim 18 , wherein Vdata1>Vdata2.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (16)