Semiconductor package including stacked semiconductor chips

1. A semiconductor package comprising:

a substrate having a first side and a second side, the first and second sides being on opposite sides of the substrate in a first direction;

a first semiconductor chip disposed over the substrate;

a first one-side third semiconductor chip stack disposed over the substrate and spaced apart from the first semiconductor chip, the first one-side third semiconductor chip stack being closer to the first side than the first semiconductor chip;

a second semiconductor chip stack disposed over the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including at least two second semiconductor chips; and

a second one-side third semiconductor chip stack disposed over the second semiconductor chip stack;

wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the plurality of third semiconductor chips are farther from the substrate, so that chip pads that are disposed on other-side edge regions of the plurality of the third semiconductor chips are exposed;

wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack is electrically connected to the substrate through a bonding wire that extends to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other;

wherein the second semiconductor chip stack includes a volatile memory;

wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a non-volatile memory; and

wherein the first semiconductor chip includes a memory controller.

2. The semiconductor package according to claim 1 , further comprising:

a plurality of power connection electrodes disposed under the substrate that are for supplying power to the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack,

wherein the plurality of power connection electrodes are closer to the second side of the substrate than to the first side of the substrate.

3. The semiconductor package according to claim 2 , wherein the substrate further comprises:

a first one-side wiring structure connecting the bonding wire that is connected to the first one-side third semiconductor chip stack to a first corresponding power connection electrode, among the plurality of power connection electrodes; and

a second one-side wiring structure connecting the bonding wire that is connected to the second one-side third semiconductor chip stack to a second corresponding power connection electrode, among the plurality of power connection electrodes.

4. The semiconductor package according to claim 1 , further comprising:

a dummy semiconductor chip disposed in a space between the substrate and the second semiconductor chip stack and disposed to be adjacent to the first one-side third semiconductor chip stack and the first semiconductor chip.

5. The semiconductor package according to claim 1 , wherein the second semiconductor chip stack partially overlaps with the first semiconductor chip and the second one-side third semiconductor chip stack to provide a first space between the first semiconductor chip and the second one-side third semiconductor chip stack in a vertical direction, and

wherein the semiconductor package further comprises a first dummy semiconductor chip disposed in the first space.

6. The semiconductor package according to claim 5 , further comprising:

a second dummy semiconductor chip disposed in a second space between the substrate and the second one-side third semiconductor chip stack in the vertical direction and is adjacent to the first semiconductor chip and the second semiconductor chip stack.

7. The semiconductor package according to claim 6 , wherein a thickness of the second dummy semiconductor chip is greater than a thickness of the first dummy semiconductor chip.

8. The semiconductor package according to claim 1 , wherein, in a vertical direction, an upper surface of the first semiconductor chip and an upper surface of the first one-side third semiconductor chip stack are positioned at the same level.

9. The semiconductor package according to claim 1 , wherein, in a vertical direction, an upper surface of the first one-side third semiconductor chip stack is positioned below an upper surface of the first semiconductor chip.

10. The semiconductor package according to claim 9 , further comprising:

a dummy semiconductor chip disposed over the first one-side third semiconductor chip stack,

wherein an upper surface of the dummy semiconductor chip and the upper surface of the first semiconductor chip are positioned at the same level in the vertical direction.

11. The semiconductor package according to claim 1 , wherein, in the first direction, a width of the second semiconductor chip stack is greater than a width of the first semiconductor chip and a width of the first one-side third semiconductor chip stack.

12. The semiconductor package according to claim 11 , wherein, in a second direction that is perpendicular to the first direction, a width of the second semiconductor chip stack is greater than a width of the first semiconductor chip and less than a width of each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack, and

wherein at least two second semiconductor chip stacks are arranged in the second direction.

13. A semiconductor package comprising:

a substrate having a first side and a second side, the first and second sides being on opposite sides of the substrate in a first direction;

a first semiconductor chip disposed over the substrate;

a first one-side third semiconductor chip stack disposed over the substrate and spaced apart from the first semiconductor chip, the first one-side third semiconductor chip stack being closer to the first side than the first semiconductor chip;

a second semiconductor chip stack disposed over the first one-side third semiconductor chip stack, the second semiconductor chip stack including at least two second semiconductor chips; and

a second one-side third semiconductor chip stack disposed over the first semiconductor chip;

wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the plurality of third semiconductor chips are farther from the substrate, so that chip pads that are disposed on other-side edge regions of the plurality of the third semiconductor chips are exposed;

wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack is electrically connected to the substrate through a bonding wire that extends to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other;

wherein the second semiconductor chip stack includes a volatile memory;

wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a non-volatile memory; and

wherein the first semiconductor chip includes a memory controller.

14. The semiconductor package according to claim 13 , further comprising:

a plurality of power connection electrodes disposed under the substrate that are for supplying power to the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack,

wherein the plurality of power connection electrodes are closer to the second side of the substrate than to the first side of the substrate.

15. The semiconductor package according to claim 14 , wherein the substrate further comprises:

a first one-side wiring structure connecting the bonding wire that is connected to the first one-side third semiconductor chip stack to a first corresponding power connection electrode, among the plurality of power connection electrodes; and

a second one-side wiring structure connecting the bonding wire that is connected to the second one-side third semiconductor chip stack to a second corresponding plurality of power connection electrode, among the plurality of power connection electrodes.

16. A semiconductor package comprising:

a substrate having a first side and a second side, the first and second sides being on opposite sides of the substrate in a first direction;

a first semiconductor chip disposed over the substrate;

a first one-side third semiconductor chip stack disposed over the substrate and spaced apart from the first semiconductor chip, the first one-side third semiconductor chip stack being closer to the first side than the first semiconductor chip;

a second semiconductor chip stack disposed over the first one-side third semiconductor chip stack, the second semiconductor chip stack including at least two second semiconductor chips; and

a second one-side third semiconductor chip stack disposed over the first semiconductor chip;

wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the plurality of third semiconductor chips are farther from the substrate, so that chip pads that are disposed on other-side edge regions of the plurality of the third semiconductor chips are exposed;

wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack is electrically connected to the substrate through a bonding wire that extends to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other; and

wherein the second one-side third semiconductor chip stack is spaced apart from the second semiconductor chip stack in the first direction.

17. The semiconductor package according to claim 13 , wherein the second one-side third semiconductor chip stack is in direct contact with an upper surface of the first semiconductor chip.

18. The semiconductor package according to claim 13 , further comprising:

a dummy semiconductor chip disposed in a space between the substrate and the second one-side third semiconductor chip stack in a vertical direction and is adjacent to the first semiconductor chip.