Granted Patent B2

US 12,446,224 · App. 18/507,505 · Granted Oct 14, 2025

Inventor: Kang Sik Choi (Seongnam-si, KR)

Assignee: SK hynix Inc.

H10B43/27H01L21/76805H01L21/76816H01L21/76877H01L21/76895H01L23/5226H01L23/5283H01L23/535H10B41/27H10B41/35H10B41/41H10B43/35H10B43/40

Abstract

Claims (39)

1. A semiconductor device comprising:

a lower structure including transistors and interconnection structures respectively connected to the transistors;

a gate stack structure disposed over a portion of the lower structure;

a first semiconductor pattern disposed between the lower structure and the gate stack structure, wherein the gate stack structure includes a cell array region over the first semiconductor pattern and a contact region protruding farther laterally than the first semiconductor pattern from the cell array region;

a second semiconductor pattern disposed between the lower structure and the contact region of the gate stack structure;

a lower contact plug disposed between the second semiconductor pattern and a corresponding interconnection structure, among the interconnection structures;

a contact plug passing through the contact region of the gate stack structure and the second semiconductor pattern to be in contact with the lower contact plug; and

an insulating layer interposed between the contact plug and the gate stack structure and extending between the contact plug and the second semiconductor pattern.

2. A semiconductor memory device, comprising:

a lower contact plug;

a semiconductor pattern disposed over the lower contact plug, the semiconductor pattern including a first semiconductor layer, a first protective layer, a sacrificial layer, a second protective layer, and a second semiconductor layer;

a gate stack structure disposed over the semiconductor pattern and including a cell array region and a stepped region extending from the cell array region;

a channel structure passing through the cell array region of the gate stack structure;

a memory layer surrounding a sidewall of the channel structure;

a first contact plug disposed in the stepped region of the gate stack structure; and

an insulating layer surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure,

wherein the first contact plug passes through the insulating layer and the semiconductor pattern to contact the lower contact plug.

3. The semiconductor memory device of claim 2 , wherein the first semiconductor layer, the first protective layer, the sacrificial layer, the second protective layer, and the second semiconductor layer of the semiconductor pattern are sequentially stacked over the lower contact plug.

4. The semiconductor memory device of claim 2 , wherein the first semiconductor layer and the second semiconductor layer of the semiconductor pattern include a doped silicon layer.

5. The semiconductor memory device of claim 2 , wherein the first protective layer and the second protective layer of the semiconductor pattern include a material having a different etch rate from the sacrificial layer.

6. The semiconductor memory device of claim 2 , wherein the sacrificial layer of the semiconductor pattern includes a silicon layer.

7. The semiconductor memory device of claim 2 , wherein the first semiconductor layer, the first protective layer, the sacrificial layer, the second protective layer, and the second semiconductor layer of the semiconductor pattern surround the first contact plug.

8. The semiconductor memory device of claim 2 , wherein the lower contact plug is connected to a transistor included in a peripheral circuit via an interconnection structure.

9. The semiconductor memory device of claim 2 , wherein a width of the semiconductor pattern is greater than a width of the first contact plug.

10. The semiconductor memory device of claim 2 , further comprising:

a channel coupling pattern disposed under the cell array region of the gate stack structure; and

two semiconductor layers with the channel coupling pattern interposed between the two semiconductor layers,

wherein one of the two semiconductor layers is disposed at a level where the first semiconductor layer is disposed, and another of the two semiconductor layers is disposed at a level where the second semiconductor layer is disposed.

11. The semiconductor memory device of claim 10 , wherein the channel structure extends into the channel coupling pattern and the two semiconductor layers.

12. The semiconductor memory device of claim 11 , wherein the memory layer is divided into a first memory pattern and a second memory pattern,

wherein the first memory pattern covers a bottom of the channel structure,

wherein the second memory pattern is disposed between the channel structure and the gate stack structure, and

wherein the channel coupling pattern extends between the first memory pattern and the second memory pattern to contact the channel structure.

13. The semiconductor memory device of claim 2 , wherein the insulating layer includes an oxide layer.

14. The semiconductor memory device of claim 2 , wherein the gate stack structure includes a first stack structure and a second stack structure on the first stack structure,

wherein the gate stack structure further includes a hole having an undercut region at a boundary between the first stack structure and the second stack structure, and

wherein the memory layer and the channel structure are disposed in the hole.

15. The semiconductor memory device of claim 2 , further comprising a dummy stack structure disposed at a level where the gate stack structure is disposed, the dummy stack structure including dummy interlayer insulating layers and sacrificial layers alternately stacked with each other.

16. The semiconductor memory device of claim 15 , further comprising a second contact plug passing through the dummy stack structure.

Assignments (1)

Priority Claims (1)

Continuity (3)

References Cited (31)