Semiconductor device
A semiconductor device is provided in the present disclosure. The semiconductor device includes a substrate, a plurality of fins formed on the substrate, a dummy gate structure formed across the plurality of fins and on the substrate, a first sidewall spacer formed on a sidewall of the dummy gate structure, an interlayer dielectric layer formed on a surface portion of each fin adjacent to the first sidewall spacer to cover a lower portion of a sidewall of the first sidewall spacer, and a second sidewall spacer formed on a top of the interlayer dielectric layer and covering a remaining portion of the sidewall of the first sidewall spacer. The top of the second sidewall spacer is coplanar with a top of the first sidewall spacer and the top of the dummy gate structure.
1. A semiconductor device, comprising:
a substrate;
a plurality of fins, formed on the substrate;
a dummy gate structure, formed across the plurality of fins and on the substrate;
a first sidewall spacer, formed on a sidewall of the dummy gate structure;
an interlayer dielectric layer, formed on a surface portion of each fin adjacent to the first sidewall spacer to cover a lower portion of a sidewall of the first sidewall spacer;
a second sidewall spacer, formed on a top of the interlayer dielectric layer and covering a remaining portion of the sidewall of the first sidewall spacer, wherein the top of the second sidewall spacer is coplanar with a top of the first sidewall spacer and the top of the dummy gate structure, and the interlayer dielectric layer isolates the second sidewall spacer from an adjacent fin of the plurality of fins; and
a source region and a drain region, formed in the fins on sides of the dummy gate structure, wherein each of the source region and the drain region is formed passing through an entire thickness of the interlayer dielectric layer that is located on the surface portion of each fin.
2. The device according to claim 1 , wherein:
the first sidewall spacer includes a single-layer structure or a stacked-layer structure.
3. The device according to claim 2 , wherein:
the first sidewall spacer is made of a material including silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, or a combination thereof.
4. The device according to claim 1 , wherein:
a thickness of the first sidewall spacer is about 3 nm to about 8 nm.
5. The device according to claim 1 , wherein:
the second sidewall spacer includes a single-layer structure or a stacked-layer structure.
6. The device according to claim 5 , wherein:
the second sidewall spacer is made of a material including silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, or a combination thereof.
7. The device according to claim 1 , wherein:
a thickness of the second sidewall spacer is about 2 nm to about 6 nm.
8. The device according to claim 1 , wherein:
the interlayer dielectric layer is made of a material including silicon oxide, silicon carbide, silicon oxynitride, silicon nitride, or a combination thereof.
9. The device according to claim 1 , further including:
conductive plugs, formed over the source/drain region.
10. The device according to claim 1 , wherein:
each of the source region and the drain region is located on a side of the second sidewall spacer away from the dummy gate structure.
11. The device according to claim 1 , wherein the dummy gate structure includes a dummy gate dielectric layer and a dummy gate electrode layer.
12. A semiconductor device, comprising: The device according
a substrate;
a plurality of fins, formed on the substrate;
a dummy gate structure, formed across the plurality of fins and on the substrate;
a first sidewall spacer, formed on a sidewall of the dummy gate structure;
an interlayer dielectric layer, formed on a surface portion of each fin adjacent to the first sidewall spacer to cover a lower portion of a sidewall of the first sidewall spacer; and
a second sidewall spacer, formed on a top of the interlayer dielectric layer and covering a remaining portion of the sidewall of the first sidewall spacer, wherein the top of the second sidewall spacer is coplanar with a top of the first sidewall spacer and the top of the dummy gate structure, and the interlayer dielectric layer isolates the second sidewall spacer from an adjacent fin of the plurality of fins, wherein:
the interlayer dielectric layer includes a portion formed in contact with a surface of the substrate and in the fin between the dummy gate structure and an adjacent dummy gate structure.
13. The device according to claim 12 , wherein:
source/drain regions are formed in the fins on sides of the dummy gate structure.
14. The device according to claim 13 , wherein:
each of the source region and the drain region is formed passing through an entire thickness of the interlayer dielectric layer that is located on the surface portion of each fin.
15. The device according to claim 12 , wherein:
the first sidewall spacer includes a single-layer structure or a stacked-layer structure.
16. The device according to claim 15 , wherein:
the first sidewall spacer is made of a material including silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, or a combination thereof; and/or
a thickness of the first sidewall spacer is about 3 nm to about 8 nm.
17. The device according to claim 12 , wherein:
the second sidewall spacer includes a single-layer structure or a stacked-layer structure.
18. The device according to claim 17 , wherein:
the second sidewall spacer is made of a material including silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, or a combination thereof; and/or
a thickness of the second sidewall spacer is about 2 nm to about 6 nm.
19. The device according to claim 12 , wherein:
the interlayer dielectric layer is made of a material including silicon oxide, silicon carbide, silicon oxynitride, silicon nitride, or a combination thereof.