Stacked field effect transistor structure with independent gate control between top and bottom gates
A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.
1. A semiconductor device, comprising:
a first transistor;
a first gate electrically coupled to the first transistor;
a dielectric isolation layer on top of at least a portion of the first transistor;
a second transistor on top of at least a portion of the dielectric isolation layer;
a second gate electrically coupled to the second transistor, wherein the dielectric isolation layer is disposed to isolate the first gate from the second gate; and
a first conductive contact electrically coupled to the first gate, wherein the first conductive contact is within a first lateral boundary of the first transistor and outside of a second lateral boundary of the second transistor.
2. The semiconductor device of claim 1 , further comprising a second conductive contact electrically coupled to the second gate, wherein the second conductive contact is within the first lateral boundary and within the second lateral boundary.
3. The semiconductor device of claim 1 , further comprising:
a second conductive contact electrically coupled to a first source or drain of the first transistor, wherein the second conductive contact is connected to a frontside of the first transistor; and
a third conductive contact electrically coupled to a second source or drain of the first transistor, wherein the third conductive contact is connected to the frontside of the first transistor.
4. The semiconductor device of claim 3 , further comprising:
a fourth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fourth conductive contact is connected to the frontside of the second transistor; and
a fifth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the fifth conductive contact is connected to the frontside of the second transistor.
5. The semiconductor device of claim 1 , further comprising:
a second conductive contact electrically coupled to a first source or drain of the first transistor, wherein the second conductive contact is connected to a backside of the first transistor;
a third conductive contact electrically coupled to a second source or drain of the first transistor, wherein the third conductive contact is connected to the backside of the first transistor;
a fourth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fourth conductive contact is connected to the frontside of the second transistor; and
a fifth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the fifth conductive contact is connected to the frontside of the second transistor.
6. The semiconductor device of claim 1 , further comprising stacks of nanosheets in the first transistor and in the second transistor.
7. A semiconductor device, comprising:
a first transistor;
a first gate electrically coupled to the first transistor;
a second transistor positioned on top of the first transistor;
a second gate electrically coupled to the second transistor;
a dielectric isolation layer positioned between the first gate and the second gate;
a first conductive contact electrically coupled to the first gate; and
a second conductive contact electrically coupled to the second gate, wherein a control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.
8. The semiconductor device of claim 7 , wherein the second gate is positioned on top of at least a portion of the first gate.
9. The semiconductor device of claim 7 , further comprising stacks of nanosheets in the first transistor and in the second transistor.
10. The semiconductor device of claim 9 , further comprising a gate material of the first and second gates, wherein the gate material is wrapped around the stacks of nanosheets.
11. The semiconductor device of claim 7 , further comprising:
a third conductive contact electrically coupled to a first source or drain of the first transistor, wherein the third conductive contact is connected to a frontside of the first transistor;
a fourth conductive contact electrically coupled to a second source or drain of the first transistor, wherein the fourth conductive contact is connected to the frontside of the first transistor;
a fifth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fifth conductive contact is connected to the frontside of the second transistor; and
a sixth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the sixth conductive contact is connected to the frontside of the second transistor.
12. The semiconductor device of claim 7 , further comprising:
a third conductive contact electrically coupled to a first source or drain of the first transistor, wherein the third conductive contact is connected to a backside of the first transistor;
a fourth conductive contact electrically coupled to a second source or drain of the first transistor, wherein the fourth conductive contact is connected to the backside of the first transistor;
a fifth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fifth conductive contact is connected to the frontside of the second transistor; and
a sixth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the sixth conductive contact is connected to the frontside of the second transistor.
13. The semiconductor device of claim 7 , wherein the first transistor is a nFET and the second transistor is a pFET.
14. The semiconductor device of claim 7 , wherein the first transistor is a pFET and the second transistor is a nFET.
15. A method of manufacturing a semiconductor device, comprising:
forming a first stack of nanosheets on a substrate;
forming a second stack of nanosheets on top of the first stack of nanosheets;
forming a first dummy gate adjacent the first stack of nanosheets and below a bottom nanosheet of the second stack of nanosheets;
forming a dielectric isolation layer on top of the first dummy gate and in between the first stack of nanosheets and the second stack of nanosheets;
forming a second dummy gate on top of the dielectric isolation layer and adjacent the second stack of nanosheets;
replacing the first dummy gate with a bottom gate electrically coupled to the first stack of nanosheets, wherein the first stack of nanosheets form a first transistor in cooperation with a gate material of the bottom gate;
replacing the second dummy gate with a top gate electrically coupled to the second stack of nanosheets, wherein the second stack of nanosheets form a second transistor in cooperation with a gate material of the top gate;
forming a first conductive contact electrically coupled to the bottom gate; and
forming a second conductive contact electrically coupled to the top gate, wherein a control of the bottom gate through the first conductive contact is independent of a control of the top gate through the second conductive contact.
16. The method of claim 15 , further comprising forming the first stack of nanosheets to include a width greater than a width of the second stack of nanosheets.
17. The method of claim 16 , further comprising:
recessing a lateral boundary of the second dummy gate inward, wherein the lateral boundary of the second dummy gate is within a lateral boundary of the first dummy gate; and
positioning the first conductive contact outside of a lateral boundary of the top gate and inside a lateral boundary of the bottom gate.
18. The method of claim 15 , further comprising:
forming a third conductive contact electrically coupled to a first source or drain of the first transistor, wherein the third conductive contact is connected to a frontside of the first transistor;
forming a fourth conductive contact electrically coupled to a second source or drain of the first transistor, wherein the fourth conductive contact is connected to the frontside of the first transistor;
forming a fifth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fifth conductive contact is connected to the frontside of the second transistor; and
forming a sixth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the sixth conductive contact is connected to the frontside of the second transistor.
19. The method of claim 15 , further comprising:
forming a third conductive contact electrically coupled to a first source or drain of the first transistor, wherein the third conductive contact is connected to a backside of the first transistor;
forming a fourth conductive contact electrically coupled to a second source or drain of the first transistor, wherein the fourth conductive contact is connected to the backside of the first transistor;
forming a fifth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fifth conductive contact is connected to the frontside of the second transistor; and
forming a sixth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the sixth conductive contact is connected to the frontside of the second transistor.
20. The method of claim 19 , further comprising:
forming a back end of line layer on a backside of the substrate; and
forming a wafer carrier on a backside of the back end of line layer.