Granted Patent B2

US 12,446,322 · App. 17/724,548 · Granted Oct 14, 2025

Inventors: Prantik Mahajan (Dresden, DE); Ajay (Aligarh, IN); Vishal Ganesan (Dresden, DE); Ruchil Jain (Dresden, DE); Souvick Mitra (Essex Junction, VT)

Assignee: GlobalFoundries U.S. Inc.

H10D89/713H10D84/859

Abstract

Claims (40)

1. A structure for an electrostatic discharge protection device, the structure comprising:

a semiconductor substrate having a top surface;

a first shallow trench isolation region in the semiconductor substrate;

a second shallow trench isolation region in the semiconductor substrate, the second shallow trench isolation region adjacent to the first shallow trench isolation region;

a third shallow trench isolation region in the semiconductor substrate, the third shallow trench isolation region adjacent to the second shallow trench isolation region;

a first well in the semiconductor substrate, the first well having a first conductivity type;

a second well and a third well in the first well, the second well and the third well having the first conductivity type;

a fourth well in the first well, the fourth well positioned in a lateral direction between the second well and the third well, and the fourth well having a second conductivity type opposite to the first conductivity type;

a first doped region in the second well, the first doped region having the first conductivity type, and the first doped region having a higher dopant concentration than the second well;

a second doped region in the second well, the second doped region having the second conductivity type, and the second doped region spaced in the lateral direction from the first doped region by a gap;

a third doped region in the fourth well, the third doped region having the second conductivity type;

a fourth doped region in the fourth well, the fourth doped region having the first conductivity type; and

a first electrical connection coupled to the third doped region and the fourth doped region,

wherein the first doped region and the second doped region are positioned in the lateral direction between the first shallow trench isolation region and the second shallow trench isolation region, the second well, the third well, and the fourth well are positioned in a vertical direction between the first well and the top surface of the semiconductor substrate, the second shallow trench isolation region is positioned in the lateral direction between the first doped region and the third doped region, and the third shallow trench isolation region is positioned in the lateral direction between the third doped region and the fourth doped region.

2. The structure of claim 1 wherein the first conductivity type is p-type, and the second conductivity type is n-type.

3. The structure of claim 1 wherein the first doped region is positioned adjacent to the first shallow trench isolation region, and a portion of the second well is located in the gap.

4. The structure of claim 3 further comprising:

a dielectric layer positioned on the top surface of the semiconductor substrate over the first doped region and the portion of the second well in the gap.

5. The structure of claim 1 wherein the second well is positioned in the vertical direction between the first doped region and the first well.

6. The structure of claim 1 wherein the fourth well is positioned in the vertical direction between the third doped region and the first well.

7. The structure of claim 1 further comprising:

a fifth well in the semiconductor substrate, the fifth well having the second conductivity type,

wherein the first well is positioned in the vertical direction between the fifth well and the second well, the first well is positioned in the vertical direction between the fifth well and the third well, and the first well is positioned in the vertical direction between the fifth well and the fourth well.

8. The structure of claim 7 wherein the fifth well adjoins the first well.

9. The structure of claim 1 wherein the second well, the third well, and the fourth well overlap with the first well.

10. The structure of claim 1 wherein the first doped region is electrically floating.

11. The structure of claim 10 further comprising:

a second electrical connection coupled to the first doped region.

12. The structure of claim 11 wherein the first doped region is positioned adjacent to the first shallow trench isolation region, and a portion of the second well is located in the gap.

13. The structure of claim 12 further comprising:

a dielectric layer positioned on the top surface of the semiconductor substrate over the first doped region and the portion of the second well in the gap.

14. The structure of claim 13 wherein the first conductivity type is p-type, and the second conductivity type is n-type.

15. The structure of claim 1 further comprising:

a dielectric layer positioned on the top surface of the semiconductor substrate over the first doped region and the gap.

16. The structure of claim 1 further comprising:

a second electrical connection coupled to the first doped region.

17. The structure of claim 16 wherein the first doped region is positioned adjacent to the first shallow trench isolation region, and a portion of the second well is located in the gap.

18. The structure of claim 17 further comprising:

a dielectric layer positioned on the top surface of the semiconductor substrate over the first doped region and the portion of the second well in the gap.

19. The structure of claim 18 wherein the first conductivity type is p-type, and the second conductivity type is n-type.

Assignments (1)

Continuity (1)

References Cited (26)