Method for manufacturing image sensor including forming FinFET transfer gate having a plurality of channel fins above a p-type region
A pixel sensor includes a transfer fin field effect transistor (finFET) to transfer a photocurrent from a photodiode to a drain region. The transfer finFET includes at least a portion of the photodiode, an extension region associated with the drain region, a plurality of channel fins, and a transfer gate at least partially surrounding the channel fins to control the operation of the transfer finFET. In the transfer finFET, the transfer gate is wrapped around (e.g., at least three sides) of each of the channel fins, which provides a greater surface area over which the transfer gate is enabled to control the transfer of electrons. The greater surface area results in greater control over operation of the finFET, which may reduce switching times of the pixel sensor (which enables faster pixel sensor performance) and may reduce leakage current of the pixel sensor relative to a planar transfer transistor.
1. A method of forming a pixel sensor, comprising:
forming, in a substrate, a cell p-well (CPW) region;
forming, in the substrate, a p-type region;
forming, in the substrate and above the p-type region, a plurality of channel fins for a transfer fin field effect transistor (finFET);
forming, in the substrate and within a perimeter of the CPW region, an n-type region of a photodiode;
forming, in the substrate and within the perimeter of the CPW region, a drain extension region of the transfer finFET,
wherein the plurality of channel fins couple the n-type region and the drain extension region;
forming a transfer gate above the p-type region and at least partially around the plurality of channel fins;
etching the CPW region to form an isolation structure that surrounds the n-type region, the p-type region, the drain extension region, and the transfer gate; and
connecting the transfer gate to an interconnect.
2. The method of claim 1 , wherein the transfer gate includes a work function layer.
3. The method of claim 1 , wherein forming the transfer gate comprises:
forming a bottom interface oxide layer.
4. The method of claim 3 , wherein forming the transfer gate further comprises:
forming a high-k dielectric layer over the bottom interface oxide layer.
5. The method of claim 4 , wherein forming the transfer gate further comprises:
forming a work function layer over the high-k dielectric layer.
6. A method of forming a pixel sensor, comprising:
forming, in a substrate, a cell p-well (CPW) region;
forming, in the substrate, a p-type region;
forming, in the substrate and above the p-type region, a plurality of channel fins for a transfer fin field effect transistor (finFET);
forming, in the substrate and within a perimeter of the CPW region, an n-type region of a photodiode;
forming, in the substrate and within the perimeter of the CPW region, a drain extension region of the transfer finFET,
wherein the plurality of channel fins couple the n-type region and the drain extension region;
forming a transfer gate above the p-type region and at least partially around the plurality of channel fins,
wherein the transfer gate comprises a high-k dielectric layer over a bottom interface oxide layer; and
etching the CPW region to form an isolation structure that surrounds the n-type region, the p-type region, the drain extension region, and the transfer gate.
7. The method of claim 6 , wherein forming the transfer gate comprises:
forming a titanium nitride (TiN) layer over the high-k dielectric layer.
8. A method of forming a pixel sensor, comprising:
forming, in a substrate, a cell p-well (CPW) region;
forming, in the substrate, a p-type region;
forming, in the substrate and above the p-type region, a plurality of channel fins for a transfer fin field effect transistor (finFET);
forming, in the substrate and within a perimeter of the CPW region, a drain region;
forming, in the substrate and within the perimeter of the CPW region, an n-type region of a photodiode;
forming, in the substrate and within the perimeter of the CPW region, a drain extension region of the transfer finFET,
wherein the plurality of channel fins couple the n-type region and the drain extension region;
forming a transfer gate above the p-type region and at least partially around the plurality of channel fins;
etching the CPW region to form an isolation structure that surrounds the n-type region, the p-type region, the drain extension region, the drain region, and the transfer gate;
connecting the drain region to a first interconnect; and
connecting the transfer gate to a second interconnect.
9. The method of claim 8 , further comprising:
forming a plurality of isolation regions at least partially between the plurality of channel fins; and
wherein forming the transfer gate comprises:
forming the transfer gate above the plurality of isolation regions.
10. The method of claim 9 , further comprising:
forming an oxide layer over the plurality of channel fins and over the plurality of isolation regions; and
etching the oxide layer to form a first buffer oxide region and a second buffer oxide region; and
wherein forming the transfer gate further comprises:
forming the transfer gate between the first buffer oxide region and the second buffer oxide region.
11. The method of claim 8 , further comprising:
forming a first deep n-type region of the photodiode;
forming a second deep n-type region, of the photodiode, over the first deep n-type region; and
forming another p-type region, of the photodiode, over the n-type region; and
wherein forming the n-type region comprises:
forming the n-type region over the second deep n-type region.
12. The method of claim 8 , wherein forming the transfer gate above the p-type region comprises:
forming a titanium nitride (TiN) layer over the p-type region.
13. The method of claim 12 , wherein forming the transfer gate above the p-type region further comprises:
forming a tantalum nitride (TaN) layer over the TiN layer.
14. The method of claim 13 , wherein forming the transfer gate above the p-type region further comprises:
forming another TiN layer over the TaN layer.
15. The method of claim 14 , wherein forming the transfer gate above the p-type region further comprises:
forming a titanium aluminum (TiAl) layer over the other TiN layer.
16. The method of claim 15 , wherein forming the transfer gate above the p-type region further comprises:
forming a tungsten layer over the TiAl layer.
17. The method of claim 8 , further comprising:
forming a poly oxide layer over the plurality of channel fins.
18. The method of claim 8 , further comprising:
forming another p-type region over the n-type region.
19. The method of claim 8 , further comprising:
lining the isolation structure with a field implant (FIL) layer.
20. The method of claim 19 , further comprising:
depositing an oxide layer over the FIL layer.