Offset cancellation method and method of preventing noise generated during sensing and amplification
A method for controlling a sense amplifier chronologically includes an idle phase, an offset cancellation phase, a charge sharing phase, and a sensing and amplification phase. In the charge sharing phase, the method includes controlling the first node to connect to the complementary bit line for a first predetermined duration and the second node to connect to the bit line for the first predetermined duration, and then disconnecting the connection between the bit line and the second node and the connection between the first node and the complementary bit line. In the sensing and amplification phase, the method include controlling the first node to connect to the complementary bit line and the second node to connect to the bit line, so as to transmit an amplified voltage to the bit line and the complementary bit line.
1. A method for controlling a sense amplifier, wherein the sense amplifier comprises a first N-type transistor, a second N-type transistor, a first P-type transistor, and a second P-type transistor; a drain of the first N-type transistor, a drain of the first P-type transistor, and a gate of the second P-type transistor are connected to a first node; a drain of the second N-type transistor, a drain of the second P-type transistor, and a gate of the first P-type transistor are connected to a second node; a gate of the first N-type transistor is connected to a bit line and a gate of the second N-type transistor is connected to a complementary bit line; a source of the first P-type transistor and a source of the second P-type transistor are configured to connect to a power supply voltage, and a source of the first N-type transistor and a source of the second N-type transistor are configured to connect to ground; and the method for controlling the sense amplifier chronologically comprises an idle phase, an offset cancellation phase, a charge sharing phase, and a sensing and amplification phase that occur in sequence, wherein:
in the charge sharing phase, during which an activation signal is input to a word line corresponding to a storage unit connected to the sense amplifier, controlling the first node to connect to the complementary bit line for a first predetermined duration and controlling the second node to connect to the bit line for the first predetermined duration, and then disconnecting the connection between the bit line and the second node and the connection between the first node and the complementary bit line; and
in the sensing and amplification phase, in response to detecting that a voltage on the first node or a voltage on the second node reaches a predetermined voltage, controlling the first node to connect to the complementary bit line and the second node to connect to the bit line, to transmit an amplified voltage to the bit line and the complementary bit line.
2. The method according to claim 1 , further comprising:
in the idle phase, controlling the first node, the second node, the bit line, and the complementary bit line to connect to each other and connect to a predetermined equalization voltage;
in the offset cancellation phase, disconnecting the connection between the first node and the complementary bit line, the connection between the second node and the bit line, and the connection between the predetermined equalization voltage and each of the first node, the second node, the bit line, and the complementary bit line; and
in the charge sharing phase, controlling the first node to connect to the complementary bit line for the first predetermined duration, and controlling the second node to connect to the bit line for the first predetermined duration.
3. The method according to claim 2 , further comprising, in the charge sharing phase:
controlling the first node to connect to the second node for a second predetermined duration, and then disconnecting the connection between the first node and the second node; and
after disconnecting the first node from the second node, controlling the first node to connect to the complementary bit line for the first predetermined duration and the second node to connect to the bit line for the first predetermined duration, and then disconnecting the connection between the bit line and the second node and the connection between the first node and the complementary bit line.
4. The method according to claim 3 , further comprising, in the charge sharing phase:
while controlling the first node to connect to the second node, controlling both the first node and the second node to connect to the predetermined equalization voltage; and
while disconnecting the connection between the first node and the second node, disconnecting the connection between the predetermined equalization voltage and each of the first node and the second node.
5. The method according to claim 2 , wherein the sense amplifier comprises a precharge switching transistor, a first terminal of the precharge switching transistor is connected to the predetermined equalization voltage, a second terminal of the precharge switching transistor is configured to supply the predetermined equalization voltage, and the precharge switching transistor is configured to control at least one of the first node, the second node, the bit line, and the complementary bit line to connect to the predetermined equalization voltage or disconnect from the predetermined equalization voltage.
6. The method according to claim 5 , wherein the second terminal of the precharge switching transistor is connected to the first node, or the second terminal of the precharge switching transistor is connected to the second node.
7. The method according to claim 5 , wherein the second terminal of the precharge switching transistor is connected to the bit line, or the second terminal of the precharge switching transistor is connected to the complementary bit line.
8. The method according to claim 5 , wherein the sense amplifier comprises an equalization switching transistor, a first terminal of the equalization switching transistor is connected to the first node, a second terminal of the equalization switching transistor is connected to the second node, and the equalization switching transistor is configured to control the first node to connect to the second node.
9. The method according to claim 1 , further comprising:
in both the idle phase and the charge sharing phase, controlling the source of the first P-type transistor and the source of the second P-type transistor to disconnect from the power supply voltage, and controlling the source of the first N-type transistor and the source of the second N-type transistor to disconnect from the ground; and
in both the offset cancellation phase and the sensing and amplification phase, controlling the source of the first P-type transistor and the source of the second P-type transistor to connect to the power supply voltage, and controlling the source of the first N-type transistor and the source of the second N-type transistor to connect to the power supply voltage.
10. The method according to claim 1 , wherein the sense amplifier comprises a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; a first terminal of the first switching transistor is connected to the first node, and a second terminal of the first switching transistor is connected to the complementary bit line; a first terminal of the second switching transistor is connected to the second node, and a second terminal of the second switching transistor is connected to the bit line; a first terminal of the third switching transistor is connected to the first node, and a second terminal of the third switching transistor is connected to the bit line; a first terminal of the fourth switching transistor is connected to the second node, and a second terminal of the fourth switching transistor is connected to the complementary bit line.
11. The method according to claim 10 , wherein the first switching transistor and the second switching transistor have same process parameters; in the charge sharing phase, the first switching transistor and the second switching transistor are turned on by a first voltage; in the sensing and amplification phase, a turn-on voltage of the first switching transistor and the second switching transistor gradually increases from the first voltage to a second voltage, to control the first switching transistor and the second switching transistor to be turned on; the first voltage is greater than or equal to a gate threshold voltage of the first switching transistor and the second switching transistor.
12. An electronic device, comprising:
a memory, comprising a sense amplifier and a sense amplifier control circuit,
wherein the sense amplifier comprises a first N-type transistor, a second N-type transistor, a first P-type transistor, and a second P-type transistor; a drain of the first N-type transistor, a drain of the first P-type transistor, and a gate of the second P-type transistor are connected to a first node; a drain of the second N-type transistor, a drain of the second P-type transistor, and a gate of the first P-type transistor are connected to a second node; a gate of the first N-type transistor is connected to a bit line and a gate of the second N-type transistor is connected to a complementary bit line; a source of the first P-type transistor and a source of the second P-type transistor are configured to connect to a power supply voltage, and a source of the first N-type transistor and a source of the second N-type transistor are configured to connect to ground; and
wherein the sense amplifier control circuit is configured to control the sense amplifier chronologically in an idle phase, an offset cancellation phase, a charge sharing phase, and a sensing and amplification phase that occur in sequence, wherein:
in the charge sharing phase, during which an activation signal is input to a word line corresponding to a storage unit connected to the sense amplifier, the sense amplifier control circuit is configured to control the first node to connect to the complementary bit line for a first predetermined duration and controlling the second node to connect to the bit line for the first predetermined duration, and then disconnect the connection between the bit line and the second node and the connection between the first node and the complementary bit line; and
in the sensing and amplification phase, the sense amplifier control circuit is configured to, in response to detecting that a voltage on the first node or a voltage on the second node reaches a predetermined voltage, control the first node to connect to the complementary bit line and the second node to connect to the bit line, to transmit an amplified voltage to the bit line and the complementary bit line.
13. The electronic device according to claim 12 , wherein:
in the idle phase, the sense amplifier control circuit is configured to control the first node, the second node, the bit line, and the complementary bit line to connect to each other and connect to a predetermined equalization voltage;
in the offset cancellation phase, the sense amplifier control circuit is configured to disconnect the connection between the first node and the complementary bit line, the connection between the second node and the bit line, and the connection between the predetermined equalization voltage and each of the first node, the second node, the bit line, and the complementary bit line; and
in the charge sharing phase, the sense amplifier control circuit is configured to control the first node to connect to the complementary bit line for the first predetermined duration, and controlling the second node to connect to the bit line for the first predetermined duration.
14. The electronic device according to claim 13 , wherein, in the charge sharing phase, the sense amplifier control circuit is configured to:
control the first node to connect to the second node for a second predetermined duration, and then disconnect the connection between the first node and the second node; and
after disconnecting the first node from the second node, control the first node to connect to the complementary bit line for the first predetermined duration and the second node to connect to the bit line for the first predetermined duration, and then disconnect the connection between the bit line and the second node and the connection between the first node and the complementary bit line.
15. The electronic device according to claim 14 , wherein, in the charge sharing phase, the sense amplifier control circuit is configured to:
while controlling the first node to connect to the second node, control both the first node and the second node to connect to the predetermined equalization voltage; and
while disconnecting the connection between the first node and the second node, disconnect the connection between the predetermined equalization voltage and each of the first node and the second node.
16. The electronic device according to claim 13 , wherein the sense amplifier comprises a precharge switching transistor, a first terminal of the precharge switching transistor is connected to the predetermined equalization voltage, a second terminal of the precharge switching transistor is configured to supply the predetermined equalization voltage, and the precharge switching transistor is configured to control at least one of the first node, the second node, the bit line, and the complementary bit line to connect to the predetermined equalization voltage or disconnect from the predetermined equalization voltage.
17. The electronic device according to claim 12 , wherein:
in both the idle phase and the charge sharing phase, the sense amplifier control circuit is configured to control the source of the first P-type transistor and the source of the second P-type transistor to disconnect from the power supply voltage, and control the source of the first N-type transistor and the source of the second N-type transistor to disconnect from the ground; and
in both the offset cancellation phase and the sensing and amplification phase, the sense amplifier control circuit is configured to control the source of the first P-type transistor and the source of the second P-type transistor to connect to the power supply voltage, and control the source of the first N-type transistor and the source of the second N-type transistor to connect to the power supply voltage.
18. The electronic device according to claim 12 , wherein the sense amplifier comprises a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; a first terminal of the first switching transistor is connected to the first node, and a second terminal of the first switching transistor is connected to the complementary bit line; a first terminal of the second switching transistor is connected to the second node, and a second terminal of the second switching transistor is connected to the bit line; a first terminal of the third switching transistor is connected to the first node, and a second terminal of the third switching transistor is connected to the bit line; a first terminal of the fourth switching transistor is connected to the second node, and a second terminal of the fourth switching transistor is connected to the complementary bit line.
19. The electronic device according to claim 18 , wherein the first switching transistor and the second switching transistor have same process parameters; in the charge sharing phase, the first switching transistor and the second switching transistor are turned on by a first voltage; in the sensing and amplification phase, a turn-on voltage of the first switching transistor and the second switching transistor gradually increases from the first voltage to a second voltage, to control the first switching transistor and the second switching transistor to be turned on; the first voltage is greater than or equal to a gate threshold voltage of the first switching transistor and the second switching transistor.
20. The electronic device according to claim 12 , wherein the sense amplifier control circuit is configured to amplify a voltage difference between the bit line and the complementary bit line that are connected to the sense amplifier.