Method of fabricating semiconductor devices having different architectures and semiconductor devices fabricated thereby
A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.
1. A method of manufacturing a semiconductor device based on a dual-architecture-compatible design, the method comprising:
forming one or more components of one or more transistors in a transistor (TR) layer of the semiconductor device; and
performing one of:
(A) fabricating additional components according to a buried power rail (BPR) architecture for the semiconductor device, the BPR architecture including layers below the transistor layer (sub-TR layers) and layers over the transistor layer (supra-TR layers); or
(B) fabricating additional components according to a non-buried power rail (non-BPR) architecture for the semiconductor device, the non-BPR architecture including supra-TR layers; and
wherein:
the dual-architecture-compatible design is substantially equally suitable either to adaptation into the BPR architecture or adaptation into the non-BPR architecture;
the (A) fabricating additional components according to a BPR architecture includes:
in corresponding sub-TR layers, forming various non-dummy structures (non-dummy sub-TR structures) correspondingly coupled to one or more of the one or more components of the one or more transistors; and
in corresponding supra-TR layers, forming various dummy structures (dummy supra-TR structures) which are corresponding artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the non-BPR architecture; and
the (B) fabricating additional components according to a non-BPR architecture includes:
in corresponding supra-TR layers:
forming various non-dummy structures (non-dummy supra-TR structures) correspondingly coupled to one or more of the one or more components of the one or more transistors; and
forming various dummy structures (dummy supra-TR structures) which are corresponding artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR architecture.
2. The method of claim 1 , wherein:
each of the TR layer and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the supra-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions; and
the (B) fabricating additional components according to a non-BPR architecture further includes:
relative to at least one of the first and second directions, locating the various dummy supra-TR structures asymmetrically with respect to the various non-dummy supra-TR structures; or
relative to at least one of the first or second directions, locating the various dummy supra-TR structures symmetrically with respect to the various non-dummy supra-TR structures.
3. The method of claim 1 , wherein:
each of the TR layer and the supra-TR layers extends substantially in first and second directions which are perpendicular;
at least one of (A) the supra-TR layers or (B) the sub-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions;
as viewed from the third direction, a footprint of a given structure is an area relative to the first and second directions occupied by the given structure; and
the (A) fabricating additional components according to a BPR architecture further includes:
configuring a collective footprint of the various dummy sub-TR structures to be substantially contained within a collective footprint of the corresponding TR components; or
the (B) fabricating additional components according to a non-BPR architecture further includes:
configuring a collective footprint of the various dummy supra-TR structures to be substantially contained within a collective footprint of the corresponding TR components.
4. The method of claim 1 , wherein the (A) fabricating additional components according to a BPR architecture further includes:
in corresponding ones of the sub-TR layers,
forming various dummy structures (dummy sub-TR structures) which are corresponding artifacts resulting from of the dual-architecture-compatible design being suitable to adaptation into the non-BPR architecture.
5. The method of claim 4 , wherein:
each of the TR layer, the sub-TR layers and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the sub-TR layers and the supra-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions; and
the (A) fabricating additional components according to a BPR architecture further includes:
relative to at least one of the first or second directions, locating the various dummy sub-TR structures asymmetrically with respect to the various non-dummy sub-TR structures; or
relative to at least one of the first or second directions, locating the various dummy supra-TR structures symmetrically with respect to the various non-dummy sub-TR structures.
6. The method of claim 1 , wherein:
the (A) fabricating additional components according to a BPR architecture results in the semiconductor device being:
an inductor;
a Metal-Insulator-Metal (MIM) capacitor; or
a MIM diode.
7. The method of claim 1 , wherein:
the (B) fabricating additional components according to a non-BPR architecture results in the semiconductor device being:
a decoupling capacitor circuit;
a high resistance structure;
a Metal-Oxide-Metal (MOM) capacitor;
a MOM diode;
a Metal-Insulator-Metal (MIM) capacitor; or
a MIM diode.
8. A semiconductor device comprising:
in a transistor (TR) layer, components of corresponding transistors (TR components); and
in corresponding layers over the transistor layer (supra-TR layers):
various non-dummy structures (non-dummy supra-TR structures) coupled to the TR components and which are included because the semiconductor device has a non-buried power rail (non-BPR) architecture; and
various dummy structures (dummy supra-TR structures) which are included as artifacts resulting from the semiconductor device being based on a dual-architecture-compatible design which is substantially equally suitable either to adaptation into the non-BPR architecture or adaptation into a buried power rail (BPA) architecture.
9. The semiconductor device of claim 8 , further comprising:
in corresponding layers below the transistor layer (sub-TR layers):
various dummy structures (dummy sub-TR structures) which are included as artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR architecture.
10. The semiconductor device of claim 8 , wherein:
each of the TR layer and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the supra-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions; and
relative to at least one of the first and second directions, the various dummy supra-TR structures are located asymmetrically with respect to the various non-dummy supra-TR structures.
11. The semiconductor device of claim 10 , wherein:
the semiconductor device is:
a decoupling capacitor circuit;
a high resistance structure;
a Metal-Insulator-Metal (MIM) capacitor; or
a MIM diode.
12. The semiconductor device of claim 8 , wherein:
each of the TR layer and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the supra-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions; and
relative to at least one of the first or second directions, the various dummy supra-TR structures are located symmetrically with respect to the various non-dummy supra-TR structures.
13. The semiconductor device of claim 8 , wherein:
each of the TR layer and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the supra-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions;
as viewed from the third direction, a footprint of a given structure is an area relative to the first and second directions occupied by the given structure; and
a collective footprint of the various dummy supra-TR structures is substantially contained within a collective footprint of the corresponding TR components.
14. A semiconductor device comprising:
in a transistor (TR) layer, components of corresponding transistors (transistor components); and
in corresponding layers below the transistor layer (sub-TR layers):
various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and which are included because the semiconductor device has a buried power rail (BPR) architecture; and
in corresponding layers over the transistor layer (supra-TR layers):
various dummy structures (dummy supra-TR structures) which are included as artifacts resulting from the semiconductor device being based on a dual-architecture-compatible design which is substantially equally suitable either to adaptation into the BPR architecture or adaptation into a non-BPR architecture.
15. The semiconductor device of claim 14 , further comprising:
in corresponding layers below the transistor layer:
various dummy structures (dummy sub-TR structures) which would be consistent with the semiconductor device otherwise having the non-BPR architecture.
16. The semiconductor device of claim 15 , wherein:
each of the TR layer, the sub-TR layers and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the sub-TR layers and the supra-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions; and
relative to at least one of the first or second directions, the various dummy sub-TR structures are located symmetrically with respect to the various dummy sub-TR structures.
17. The semiconductor device of claim 16 , wherein:
the semiconductor device is:
a Metal-Insulator-Metal (MIM) capacitor; or
a MIM diode.
18. The semiconductor device of claim 14 , wherein:
each of the TR layer, and the sub-TR layers and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the sub-TR layers and the supra-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions; and
relative to at least one of the first or second directions, the various dummy supra-TR structures are located asymmetrically with respect to the various non-dummy sub-TR structures.
19. The semiconductor device of claim 14 , wherein:
each of the TR layer and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the sub-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions;
as viewed from the third direction, a footprint of a given structure is an area relative to the first and second directions occupied by the given structure; and
a collective footprint of the various dummy supra-TR structures is substantially contained within a collective footprint of the corresponding transistor components.
20. The semiconductor device of claim 14 , wherein:
each of the TR layer, the sub-TR layers and the supra-TR layers extends substantially in first and second directions which are perpendicular;
the sub-TR layers and the supra-TR layers are stacked in a third direction which is substantially perpendicular to each of the first and second directions; and
relative to at least one of the first or second directions, the various dummy supra-TR structures are located asymmetrically with respect to the various non-dummy sub-TR structures.