Printed circuit board and semiconductor package using the same
Provided is a printed circuit board including a substrate structure having a first surface including a chip mounting region on which a semiconductor chip is mounted and a second surface opposite to the first surface, the second surface having a rectangular shape having a first edge, a second edge, a third edge, and a fourth edge and a first corner, a second corner, a third corner, and a fourth corner formed by the first to fourth edges, and pad patterns disposed on the second surface of the substrate structure, wherein the second surface includes a first region including a region corresponding to the chip mounting region and in contact with the first to fourth edges of the second surface, respectively, and second regions adjacent to the first to fourth corners of the second surface, respectively and spaced apart from each other by the first region, wherein the pad patterns include first pad patterns disposed in the first region and surface-treated with a nickel/gold (Ni/Au) layer, and second pad patterns disposed in the second regions and surface-treated with an organic solderability preservative.
1. A printed circuit board comprising:
a substrate structure having a first surface comprising a chip mounting region on which a semiconductor chip is mounted and a second surface opposite to the first surface, the second surface having a rectangular shape having a first edge, a second edge, a third edge, and a fourth edge and a first corner, a second corner, a third corner, and a fourth corner formed by the first to fourth edges; and
pad patterns disposed on the second surface of the substrate structure,
wherein the second surface comprises:
a first region comprising a region corresponding to the chip mounting region and in contact with the first to fourth edges of the second surface, respectively; and
second regions adjacent to the first to fourth corners of the second surface, respectively and spaced apart from each other by the first region,
wherein the pad patterns comprise:
first pad patterns disposed in the first region and surface-treated with a nickel/gold (Ni/Au) layer; and
second pad patterns disposed in the second regions and surface-treated with an organic solderability preservative (OSP), and
wherein a level of at least one lower surface of the first pad patterns that are surface-treated is lower than a level of at least one lower surface of the second pad patterns that are surface-treated.
2. The printed circuit board of claim 1 , wherein the substrate structure further comprises a passivation layer disposed on a portion of the pad patterns, the passivation layer having openings forming the pad patterns by exposing a portion of the second surface.
3. The printed circuit board of claim 2 , wherein the OSP and the nickel/gold layer are in contact with the openings, respectively.
4. The printed circuit board of claim 3 , wherein the nickel/gold layer comprises
a nickel layer in direct contact with the first pad patterns in a direction perpendicular to the second surface; and
a gold layer disposed on the nickel layer.
5. The printed circuit board of claim 2 , wherein the pad patterns comprise copper (Cu).
6. The printed circuit board of claim 1 , wherein the second pad patterns comprise pad patterns adjacent to the first to fourth corners, respectively.
7. The printed circuit board of claim 6 , wherein the second regions comprise a region extending along the first to fourth edges, respectively.
8. The printed circuit board of claim 1 , wherein the pad patterns are disposed in a matrix form having a plurality of rows and plurality of columns.
9. A printed circuit board comprising:
a substrate structure having a first surface comprising a chip mounting region on which a semiconductor chip is mounted, and a second surface opposite to the first surface; and
pad patterns disposed on the second surface of the substrate structure,
wherein the second surface comprises:
a first region comprising a region corresponding to the chip mounting region and in contact with respective edges of the second surface; and
second regions adjacent to respective corners of the second surface and spaced apart from each other,
wherein the pad patterns comprise first pad patterns surface-treated with a metal layer and second pad patterns surface-treated with an oxidation prevention layer,
wherein the first pad patterns are disposed in the first region, and the second pad patterns are disposed in the second regions, respectively, and
wherein a level of at least one lower surface of the first pad patterns surface-treated is lower than a level of at least one lower surface of the second pad patterns surface-treated.
10. The printed circuit board of claim 9 , wherein the metal layer comprises a nickel/gold (Ni/Au) layer, and
wherein an antioxidant layer comprises an organic solderability preservative.
11. The printed circuit board of claim 9 , wherein each of the second regions does not overlap the chip mounting region.
12. The printed circuit board of claim 9 , wherein the second regions are disposed rotationally symmetrically every 90° with respect to a center of the second surface.
13. The printed circuit board of claim 9 , wherein areas of the second regions are substantially the same.
14. The printed circuit board of claim 9 , wherein the second regions comprises a second pad pattern adjacent to any one of the corners among the first pad patterns, respectively.
15. A semiconductor package comprising:
a semiconductor chip;
a substrate structure having a first surface comprising a chip mounting region on which the semiconductor chip is mounted and a second surface, opposite to the first surface, the second surface having a rectangular shape having a first edge, a second edge, a third edge, and a fourth edge, and a first corner, a second corner, a third corner, and a fourth corner formed by the first to fourth edges;
pad patterns disposed on the second surface of the substrate structure; and
connection bumps respectively connected to the pad patterns,
wherein the pad patterns comprise:
first pad patterns disposed in a first region respectively adjacent to the first to fourth edges and comprising a region corresponding to the chip mounting region, in direct contact with the connection bumps, and the first pad patterns comprising a first metal material and having a metal layer comprising a second metal material disposed on an interface in contact with the connection bumps; and
second pad patterns disposed in second regions respectively adjacent to the first to fourth corners, the second regions being regions other than the first region, the second pad patterns comprising the first metal material, and
wherein a level of at least one lower surface of the first pad patterns is lower than a level of at least one lower surface of the second pad patterns.
16. The semiconductor package of claim 15 , wherein the first metal material includes copper (Cu),
wherein the second metal material includes nickel (Ni), and
wherein the connection bumps include tin (Sn).
17. The semiconductor package of claim 15 , wherein in a direction perpendicular to the second surface, each of the first pad patterns has a first thickness between an upper surface and a lower surface of each of the first pad patterns,
wherein the metal layer has a second thickness between an upper surface and a lower surface,
wherein in the perpendicular direction, each of the second pad patterns has a third thickness between an upper surface and a lower surface of each of the second pad patterns,
and
wherein a sum of the first thickness and the second thickness is greater than the third thickness.
18. The semiconductor package of claim 15 , wherein the substrate structure further comprises a passivation layer disposed on a portion of the pad patterns, and having openings forming the pad patterns by exposing a portion of the second surface, and
wherein the connection bumps are in contact with side surfaces of the openings, respectively, and are connected to the pad patterns.
19. The semiconductor package of claim 18 , further comprising a capping layer disposed on the semiconductor chip and the first surface of the substrate structure.
20. The semiconductor package of claim 18 , wherein the connection bumps are lead free solder balls.