Semiconductor device and memory device including a dummy element
A semiconductor device includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including an active region disposed on a substrate, and a gate structure intersecting the active region and extending in a first direction that is parallel to an upper surface of the substrate; and at least one dummy element disposed between a pair of semiconductor elements adjacent to each other in a second direction, intersecting the first direction, among the plurality of semiconductor elements. The dummy element includes a dummy active region and at least one dummy gate structure intersecting the dummy active region and extending in the first direction. A length of the dummy active region in the second direction is less than a length of the active region included in each of the pair of semiconductor elements.
1. A semiconductor device, comprising:
a plurality of semiconductor elements, each of the plurality of semiconductor elements including an active region disposed on a substrate, and a gate structure intersecting the active region, wherein a longest dimension of the gate structure extends in a first direction that is parallel to an upper surface of the substrate; and
at least one dummy element disposed between a pair of semiconductor elements, of the plurality of semiconductor elements, in a second direction, intersecting the first direction,
wherein the at least one dummy element includes a dummy active region and at least one dummy gate structure intersecting the dummy active region and wherein a longest dimension of the dummy gate structure extends in the first direction,
wherein the active region includes a first active region and a second active region, and the gate structure is disposed between the first active region and the second active region in the second direction,
wherein the dummy active region includes a first dummy active region and a second dummy active region, and the dummy gate structure is disposed between the first dummy active region and the second dummy active region,
wherein a length of each of the first dummy active region and the second dummy active region, in the second direction, is less than a length of each of the first active region and the second active region included in each of the pair of semiconductor elements,
wherein the second direction is a horizontal direction parallel to the upper surface of the substrate, and
wherein an entire length of the dummy active region, in the first direction, is greater than or equal to an entire length of the active region included in at least one of the pair of semiconductor elements.
2. The semiconductor device of claim 1 , wherein a length of the dummy active region, in the first direction, is equal to a length of the active region included in at least one of the pair of semiconductor elements.
3. The semiconductor device of claim 2 , wherein at least one boundary, among boundaries of the active region included in the pair of semiconductor elements, is disposed in the same position, in the first direction, as at least one boundary, among boundaries of the dummy active region.
4. The semiconductor device of claim 1 , wherein a length of the dummy active region, in the first direction, is different from a length of the active region included in each of the pair of semiconductor elements.
5. The semiconductor device of claim 4 , wherein the length of the dummy active region, in the first direction, is longer than the length of the active region included in each of the pair of semiconductor elements.
6. The semiconductor device of claim 1 , wherein, in each of the pair of semiconductor elements, the first active region provides a source region and the second active region provides a drain region disposed on opposite sides of the gate structure,
wherein in the at least one dummy element, the first dummy active region provides a dummy source region and the second dummy active region provides a dummy drain region disposed on opposite sides of the at least one dummy gate structure, and
wherein an area of each of the source region and the drain region is larger than an area of each of the dummy source region and the dummy drain region, respectively.
7. The semiconductor device of claim 6 , wherein at least one of the source region or the drain region is connected to at least one wiring pattern among wiring patterns disposed on the plurality of semiconductor elements in a third direction, perpendicular to the upper surface of the substrate, by an active contact, and
wherein the dummy source region and the dummy drain region are electrically separated from the wiring patterns.
8. The semiconductor device of claim 7 , wherein at least one of the source region or the drain region is connected to the at least one wiring pattern by two or more active contacts.
9. The semiconductor device of claim 7 , wherein dimensions of the active contact in the first and second directions are different from each other.
10. The semiconductor device of claim 9 , wherein a dimension of the active contact in the first direction is greater than a dimension of the active contact in the second direction.
11. The semiconductor device of claim 1 , wherein the plurality of semiconductor elements comprise low voltage elements disposed in a low voltage region to which a first power voltage is supplied, and high voltage elements disposed in a high voltage region to which a second power voltage, greater than the first power voltage, is supplied, and
wherein the pair of semiconductor elements are the low voltage elements.
12. The semiconductor device of claim 11 , wherein the at least one dummy element is disposed exclusively in the low voltage region.
13. The semiconductor device of claim 1 , wherein the at least one dummy gate structure comprises a pair of dummy gate structures separated from each other in the second direction.