Three-dimensional memory devices
In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
1. A device comprising:
a first conductive line extending in a first direction;
a ferroelectric layer on a sidewall of the first conductive line;
a semiconductor layer on a sidewall of the ferroelectric layer;
a first dielectric layer on a sidewall of the semiconductor layer; and
a second conductive line having a first main region and a first extension region, the first main region contacting the semiconductor layer, the first extension region separated from the semiconductor layer by the first dielectric layer, the second conductive line extending in a second direction, the second direction perpendicular to the first direction.
2. The device of claim 1 , wherein the semiconductor layer is disposed between the ferroelectric layer and an entirety of the first main region of the second conductive line.
3. The device of claim 1 , wherein the semiconductor layer is disposed between the ferroelectric layer and a portion of the first main region of the second conductive line.
4. The device of claim 1 , further comprising:
a third conductive line having a second main region and a second extension region, the second main region contacting the semiconductor layer, the second extension region separated from the semiconductor layer by the first dielectric layer, the third conductive line extending in the second direction; and
an isolation region between the third conductive line and the second conductive line.
5. The device of claim 4 , wherein the isolation region, the first extension region of the second conductive line, and the second extension region of the third conductive line have a same width in a third direction, the third direction perpendicular to the first direction and to the second direction.
6. The device of claim 4 , wherein the isolation region has a first width in the first direction and the first dielectric layer has a second width in the first direction, the second width greater than the first width.
7. The device of claim 1 , wherein the first dielectric layer comprises aluminum oxide.
8. The device of claim 1 , further comprising:
a second dielectric layer over the first conductive line; and
an interconnect connected to a portion of the first conductive line exposed by the second dielectric layer.
9. A device comprising:
a bit line extending in a first direction;
a source line extending in the first direction;
an isolation region between the source line and the bit line;
a word line extending in a second direction, the second direction perpendicular to the first direction;
a back gate isolator between the word line and each of the isolation region, a first portion of the bit line, and a second portion of the source line;
a semiconductor layer between the back gate isolator and the word line; and
a memory film between the semiconductor layer and the word line.
10. The device of claim 9 , wherein the isolation region has a first width in the second direction, and the back gate isolator has a second width in the second direction, the second width greater than the first width.
11. The device of claim 10 , wherein the semiconductor layer has the second width in the second direction.
12. The device of claim 10 , wherein the semiconductor layer has a third width in the second direction, the third width greater than the second width.
13. The device of claim 10 , further comprising:
a source line interconnect over and connected to the source line; and
a bit line interconnect over and connected to the bit line.
14. The device of claim 10 , wherein the back gate isolator comprises aluminum oxide.
15. A device comprising:
a memory cell comprising a thin film transistor, the thin film transistor comprising:
a gate comprising a portion of a first conductive line and a portion of a memory film, the memory film disposed on a sidewall of the first conductive line, the first conductive line extending in a first direction;
a channel region comprising a portion of a semiconductor layer, the semiconductor layer disposed on a sidewall of the memory film; and
a source/drain region comprising a portion of a second conductive line, the second conductive line disposed on a sidewall of the semiconductor layer, the second conductive line extending in a second direction, the second direction perpendicular to the first direction, the second conductive line having a first T-shaped cross-section.
16. The device of claim 15 , further comprising:
a back gate isolator between the semiconductor layer and an extension region of the second conductive line.
17. The device of claim 16 , further comprising:
an isolation region, the back gate isolator disposed between the isolation region and the semiconductor layer.
18. The device of claim 16 , wherein a width of the semiconductor layer is greater than a width of the back gate isolator.
19. The device of claim 16 , wherein a width of the semiconductor layer is equal to a width of the back gate isolator.
20. The device of claim 16 , wherein the back gate isolator comprises aluminum oxide.