Redundant bottom pad and sacrificial via contact for process induced RRAM forming
A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.
1. A resistive memory comprising:
a bottom electrode;
a first contact on the bottom electrode;
a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide;
a top electrode on the switching material pad;
a plurality of sacrificial vias contacting the bottom electrode;
a second contact that is connected to the bottom electrode; and
a third contact that is connected to the top electrode.
2. The resistive memory of claim 1 , further comprising:
a substrate;
an interlevel dielectric layer on the substrate; and
a transistor in the interlevel dielectric layer, wherein the transistor comprises:
a source terminal;
a drain terminal; and
a gate terminal,
wherein the third contact is electrically connected to the transistor.
3. The resistive memory of claim 2 , wherein the third contact is electrically connected to the drain terminal of the transistor.
4. The resistive memory of claim 1 , further comprising a bottom plate, wherein the bottom electrode extends from the bottom plate, wherein the bottom plate is connected to a plurality of bottom electrodes, including the bottom electrode.
5. The resistive memory of claim 1 , further comprising a bottom plate, wherein the bottom electrode is connected to the bottom plate by a metal lead configured to limit a current supplied to a memory cell comprising the switching material pad.
6. The resistive memory of claim 1 , wherein the plurality of sacrificial vias comprise:
a passivation liner; and
an insulating material fill on the passivation liner.
7. A resistive memory comprising:
a substrate;
an interlevel dielectric layer on the substrate;
a transistor in the interlevel dielectric layer;
a bottom electrode;
a first contact on the bottom electrode;
a switching material pad on the first contact, wherein the switching material pad includes a plurality of current conducting filaments;
a top electrode on the switching material pad;
a plurality of sacrificial vias contacting the bottom electrode;
a second contact that is connected to the bottom electrode; and
a third contact that is connected to the top electrode, wherein the third contact is electrically connected to the transistor.
8. The resistive memory of claim 7 , wherein the transistor comprises:
a source terminal;
a drain terminal; and
a gate terminal.
9. The resistive memory of claim 8 , wherein the third contact is electrically connected to the drain terminal of the transistor.
10. The resistive memory of claim 7 , further comprising a bottom plate, wherein the bottom electrode extends from the bottom plate.
11. The resistive memory of claim 10 , wherein the bottom plate is connected to a plurality of bottom electrodes, including the bottom electrode.
12. The resistive memory of claim 10 , further comprising a bottom plate, wherein the bottom electrode is connected to the bottom plate by a metal lead configured to limit a current supplied to a memory cell comprising the switching material pad.
13. The resistive memory of claim 7 , further comprising:
a bottom electrode plate; and
a plurality of bottom electrode lines, wherein a first bottom electrode line of the plurality of bottom electrode lines is connected to the bottom electrode.
14. The resistive memory of claim 7 , wherein the first contact is above the interlevel dielectric layer.
15. The resistive memory of claim 7 , wherein the plurality of sacrificial vias comprise:
a passivation liner; and
an insulating material fill on the passivation liner.
16. The resistive memory of claim 7 , wherein the switching material pad includes an oxide.