IP Library › Granted Patent US 12,364,173
Granted Patent B2
US 12,364,173 · App. 17/517,724 · Granted Jul 15, 2025

Resistive memory cell using an interfacial transition metal compound layer and method of forming the same

Inventors: Wen-Hao Cheng (Taichung, TW); Yuan-Huang Lee (Hsinchu, TW); Yu-Wen Liao (New Taipei, TW); Yen-Yu Chen (Taichung, TW); Hsuan-Chih Chu (Changhua County, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
H10N70/841H10B63/30H10B63/80H10N70/063H10N70/24H10N70/826H10N70/8833H10N70/8836
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Quick Facts
Patent No.
US 12,364,173
App. No.
17/517,724
Granted
Jul 15, 2025
Kind
B2
Abstract

A resistive memory cell includes a lower electrode, a resistive transition metal oxide layer, and an upper electrode. The lower electrode includes at least one lower metallic barrier layer, a lower metal layer including a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer including an oxide or nitride of a transition metal selected from Ti, Ta, and W. The resistive transition metal oxide layer includes a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer. The upper electrode includes an upper metal layer including a second metal having a melting point higher than 2,000 degrees Celsius and at least one upper metallic barrier layer.

Claims (49)

1. A device structure comprising a resistive memory cell, wherein the resistive memory cell comprises:

a lower electrode comprising at least one lower metallic barrier layer, a lower metal layer comprising a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer comprising an oxide or nitride of a transition metal selected from Ti, Ta, and W;

a resistive transition metal oxide layer comprising a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer; and

an upper electrode comprising an upper metal layer comprising a second metal.

2. The device structure of claim 1 , wherein the transition metal compound layer comprises a transition metal oxide material selected from titanium oxide and tantalum oxide.

3. The device structure of claim 1 , wherein the transition metal compound layer comprises a transition metal nitride material selected from titanium nitride, tantalum nitride, and tungsten nitride.

4. The device structure of claim 1 , wherein an entirety of a top surface of the transition metal compound layer is in contact with an entirety of a bottom surface of the resistive transition metal oxide layer.

5. The device structure of claim 1 , wherein the conductive-filament-forming dielectric oxide comprises a material selected from hafnium oxide, zirconium oxide, titanium oxide, hafnium zirconium oxide, and strontium cobalt oxide.

6. The device structure of claim 1 , wherein the resistive memory cell comprises a dielectric spacer laterally surrounding the upper electrode.

7. The device structure of claim 6 , wherein:

an entirety of a bottom surface of the upper metal layer contacts a center portion of a top surface of the resistive transition metal oxide layer; and

an entirety of a bottom surface of the dielectric spacer contacts a peripheral portion of the top surface of the resistive transition metal oxide layer.

8. The device structure of claim 6 , wherein the resistive memory cell comprises a dielectric cap contacting a top surface of the upper electrode, wherein a periphery of a bottom surface of the dielectric cap coincides with a periphery of a top surface of the upper electrode.

9. The device structure of claim 8 , further comprising:

a dielectric material layer laterally surrounding the resistive memory cell and having a top surface located above a horizontal top surface of the dielectric cap; and

an upper connection via structure vertically extending through the dielectric material layer and the dielectric cap and contacting a top surface of the upper electrode.

10. The device structure of claim 1 , further comprising a dielectric etch stop layer including an opening, wherein:

a center portion of the lower electrode is located within the opening;

a peripheral portion of the lower electrode is locate outside the opening above a top surface of the dielectric etch stop layer; and

a cylindrical connection portion of the lower electrode contacts a sidewall of the opening and vertically extends between the center portion of the lower electrode and the peripheral portion of the lower electrode.

11. The device structure of claim 10 , wherein the transition metal compound layer comprises:

a bottom surface including a planar central bottom surface segment located within an area of the opening through the dielectric etch stop layer, a planar peripheral bottom surface segment located outside the area of the opening through the dielectric etch stop layer, and a concave connecting bottom surface segment that connects the planar central bottom surface segment and the planar peripheral bottom surface segment; and

a top surface including a planar central top surface segment located within an area of the opening through the dielectric etch stop layer, a planar peripheral top surface segment located outside the area of the opening through the dielectric etch stop layer, and a convex connecting top surface segment that connects the planar central top surface segment and the planar peripheral top surface segment.

12. The device structure of claim 1 , wherein:

the first metal comprises an element selected from ruthenium, tantalum, tungsten, rhenium, niobium, molybdenum, osmium, and iridium; and

the second metal comprises an element selected from ruthenium, tantalum, tungsten, rhenium, niobium, molybdenum, osmium, and iridium.

13. The device structure of claim 1 , wherein:

the at least one lower metallic barrier layer comprises a lower vertical stack including, from bottom to top, a first lower tantalum nitride layer, a lower tantalum layer, and a second lower tantalum nitride layer; and

the upper electrode comprises at least one upper metallic barrier layer, which comprises an upper vertical stack including, from bottom to top, an upper tantalum nitride layer and a titanium nitride layer.

14. A device structure comprising a resistive memory cell, wherein the resistive memory cell comprises:

a lower electrode comprising at least one lower metallic barrier layer, a lower metal layer comprising a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer comprising an oxide or nitride of a transition metal selected from Ti, Ta, and W;

a resistive transition metal oxide layer comprising a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer;

an upper electrode comprising an upper metal layer comprising a second metal; and

a dielectric spacer laterally surrounding the upper electrode, wherein a bottom periphery of an outer sidewall of the dielectric spacer coincides with a periphery of a top surface of the resistive transition metal oxide layer.

15. The device structure of claim 14 , wherein the bottom periphery of the outer sidewall of the dielectric spacer is laterally offset outward from a bottom periphery of an inner sidewall of the dielectric spacer by a uniform lateral offset distance.

16. The device structure of claim 14 , wherein the resistive transition metal oxide layer comprises:

a peripheral portion in contact with the dielectric spacer;

a center portion that is vertically recessed relative to the peripheral portion; and

a tapered annular connecting portion that connects the peripheral portion and the center portion.

17. The device structure of claim 14 , wherein the upper metal layer comprises downward protrusion at a center region thereof, wherein the downward protrusion extends below a horizontal plane including an annular horizontal bottom surface of a peripheral portion of the resistive transition metal oxide layer.

18. The device structure of claim 14 , wherein the conductive-filament-forming dielectric oxide comprises a material selected from hafnium oxide, zirconium oxide, titanium oxide, hafnium zirconium oxide, and strontium cobalt oxide.

19. A device structure comprising a resistive memory cell, wherein the resistive memory cell comprises:

a dielectric etch stop layer including an opening therethrough;

a lower electrode comprising at least one lower metallic barrier layer, a lower metal layer comprising a first metal having a melting point higher than 2,000 degrees Celsius, and a transition metal compound layer comprising an oxide or nitride of a transition metal selected from Ti, Ta, and W, wherein the lower electrode comprises a peripheral portion overlying the dielectric etch stop layer and a center portion located within the opening in the dielectric etch stop layer;

a resistive transition metal oxide layer comprising a conductive-filament-forming dielectric oxide of at least one transition metal and located on the transition metal compound layer; and

an upper electrode comprising an upper metal layer comprising a second metal.

20. The device structure of claim 19 , wherein the transition metal compound layer comprises:

a bottom surface including a planar central bottom surface segment located within an area of the opening through the dielectric etch stop layer, a planar peripheral bottom surface segment located outside the area of the opening through the dielectric etch stop layer, and a concave connecting bottom surface segment that connects the planar central bottom surface segment and the planar peripheral bottom surface segment; and

a top surface including a planar central top surface segment located within an area of the opening through the dielectric etch stop layer, a planar peripheral top surface segment located outside the area of the opening through the dielectric etch stop layer, and a convex connecting top surface segment that connects the planar central top surface segment and the planar peripheral top surface segment.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2022
From: CHENG, WEN-HAO; LEE, YUAN-HUANG; LIAO, YU-WEN; CHEN, YEN-YU; CHU, HSUAN-CHIH
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 058613/0507 →
Continuity (2)
Provisional Application 63135089 · Jan 8, 2021
Related Publication 20220223788A1 · Jul 14, 2022
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