Low-dropout regulator
A low-dropout (LDO) regulator having an analog low-dropout (ALDO) regulating circuit assisted by a digital low-dropout (DLDO) regulating circuit is shown. The DLDO regulating circuit is coupled to the ALDO regulating circuit, and senses operating information that shows if the ALDO regulating circuit is within its operating region. The DLDO regulating circuit assists the ALDO regulating circuit based on the operating information of the ALDO regulating circuit instead of an output voltage at the output terminal of the LDO regulator.
1. A low-dropout regulator, comprising:
an analog low-dropout regulating circuit; and
a digital low-dropout regulating circuit, assisting the analog low-dropout regulating circuit;
wherein:
the digital low-dropout regulating circuit is coupled to the analog low-dropout regulating circuit, and the digital low-dropout regulating circuit senses operating information that shows if the analog low-dropout regulating circuit is within its operating region;
the digital low-dropout regulating circuit assists the analog low-dropout regulating circuit based on the operating information of the analog low-dropout regulating circuit instead of an output voltage at an output terminal of the low-dropout regulator;
the analog low-dropout regulating circuit has a capacitor array providing an adaptive capacitance between a voltage source and a gate terminal of a power MOS of the analog low-dropout regulating circuit; and
the greater a current that the digital low-dropout regulating circuit provides to a load coupled to the output terminal of the low-dropout regulator, the smaller the capacitance that the capacitor array provides between the voltage source and the gate terminal of the power MOS.
2. The low-dropout regulator as claimed in claim 1 , wherein:
the digital low-dropout regulating circuit senses a current of the power MOS of the analog low-dropout regulating circuit to assist the analog low-dropout regulating circuit based on the current of the power MOS of the analog low-dropout regulating circuit.
3. The low-dropout regulator as claimed in claim 2 , further comprising:
a current-sensing MOS; and
a current-sensing resistor;
wherein:
the current-sensing MOS has a source terminal coupled to a source terminal of the power MOS, and a gate terminal coupled to a gate terminal of the power MOS;
the current-sensing resistor is coupled at a drain terminal of the current-sensing MOS; and
a connection terminal between the current-sensing MOS and the current-sensing resistor is coupled to the digital low-dropout regulating circuit and thereby the digital low-dropout regulating circuit senses the current of the power MOS.
4. The low-dropout regulator as claimed in claim 1 , wherein:
the digital low-dropout regulating circuit senses a gate voltage of the power MOS of the analog low-dropout regulating circuit to assist the analog low-dropout regulating circuit based on the gate voltage of the power MOS of the analog low-dropout regulating circuit.
5. The low-dropout regulator as claimed in claim 1 , wherein:
the digital low-dropout regulating circuit receives a sensed voltage that is the operating information that shows if the analog low-dropout regulating circuit is within its operating region;
the digital low-dropout regulating circuit has a controller;
when determining that the sensed voltage is greater than an upper limit voltage, the controller reinforces the digital low-dropout regulating circuit to provide more current to a load coupled to the output terminal of the low-dropout regulator until the sensed voltage is lower than a medium threshold voltage; and
the medium threshold voltage is lower than the upper limit voltage.
6. The low-dropout regulator as claimed in claim 5 , wherein:
when determining that the sensed voltage is lower than a lower limit voltage, the controller weakens the digital low-dropout regulating circuit to provide less current to the load until the sensed voltage is greater than the medium threshold voltage; and
the medium threshold voltage is greater than the lower limit voltage.
7. The low-dropout regulator as claimed in claim 6 , wherein the digital low-dropout regulating circuit further comprises:
a first comparator, comparing the sensed voltage with the upper limit voltage, and having an output terminal coupled to the controller;
a second comparator, comparing the sensed voltage with the medium threshold voltage, and having an output terminal coupled to the controller; and
a third comparator, comparing the sensed voltage with the lower limit voltage, and having an output terminal coupled to the controller.
8. The low-dropout regulator as claimed in claim 7 , wherein:
when the first comparator shows that the sensed voltage exceeds the upper limit voltage, the controller changes to operate according to the second comparator; and
when the third comparator shows that the sensed voltage drops lower than the lower limit voltage, the controller changes to operate according to the second comparator; and
when the second comparator shows that the sensed voltage has been regulated to the medium threshold voltage, the controller changes to operate according to the first and third comparators.
9. The low-dropout regulator as claimed in claim 6 , wherein the digital low-dropout regulating circuit further comprises:
a first comparator, comparing the sensed voltage with the upper limit voltage in a first mode, and comparing the sensed voltage with the medium threshold voltage in a second mode, wherein the first comparator has an output terminal coupled to the controller; and
a second comparator, comparing the sensed voltage with the lower limit voltage in a first mode, and comparing the sensed voltage with the medium threshold voltage in a second mode, wherein the second comparator has an output terminal coupled to the controller.
10. The low-dropout regulator as claimed in claim 9 , wherein:
when the first comparator in its first mode shows that the sensed voltage exceeds the upper limit voltage, the controller changes the first comparator to its second mode;
when the second comparator in its first mode shows that the sensed voltage drops lower than the lower limit voltage, the controller changes the second comparator to its second mode;
when the first comparator in its second mode shows that the sensed voltage has been regulated to the medium threshold voltage, the controller changes the first comparator back to its first mode; and
when the second comparator in its second mode shows that the sensed voltage has been regulated to the medium threshold voltage, the controller changes the second comparator back to its first mode.
11. The low-dropout regulator as claimed in claim 1 , wherein:
the digital low-dropout regulating circuit receives a sensed voltage that is the operating information that shows if the analog low-dropout regulating circuit is within its operating region;
the digital low-dropout regulating circuit has a controller and an analog-to-digital converter;
the analog-to-digital converter converts the sensed voltage into a digital code; and
according to the digital code, the controller changes a current that the digital low-dropout regulating circuit provides to a load coupled to the output terminal of the low-dropout regulator.
12. The low-dropout regulator as claimed in claim 1 , wherein:
the digital low-dropout regulating circuit has an array of power switches which passes an adaptive current to a load coupled to the output terminal of the low-dropout regulator, and each power switch is coupled to a PMOS that mirrors a constant current to the corresponding power switch.
13. The low-dropout regulator as claimed in claim 12 , wherein:
the digital low-dropout regulating circuit further has a capacitor coupled between the voltage source and gate terminals of the PMOSs.
14. The low-dropout regulator as claimed in claim 1 , wherein:
the digital low-dropout regulating circuit has an array of power switches which passes an adaptive current to a load coupled to the output terminal of the low-dropout regulator;
the analog low-dropout regulating circuit has an operational amplifier, having a negative input terminal receiving a reference voltage, a positive input terminal receiving the output voltage, and an output terminal coupled to a gate terminal of the power MOS of the analog low-dropout regulating circuit; and
the power MOS of the analog low-dropout regulating circuit is coupled between the voltage source and the output terminal of the low-dropout regulator.