Memory system and operating method thereof for allocating and storing meta data
A memory system includes: a memory device including a plurality of memory blocks each including a plurality of pages; and a memory controller configured to allocate, to a meta page among the plurality of pages, a first region including regions configured to store plural pieces of meta data respectively according to types of the plural pieces of meta data, and a second region configured to store additional meta data corresponding to at least one meta data among the plural pieces of meta data is stored, and control the memory device to store the plural pieces of meta data and the additional meta data in the first region and the second region, respectively.
1. A memory system comprising:
a memory device including a plurality of memory blocks each including a plurality of pages; and
a memory controller configured to:
allocate, to a meta page among the plurality of pages, a first region including regions configured to store plural pieces of meta data respectively according to types of the plural pieces of meta data, and a second region configured to store additional meta data corresponding to at least one meta data among the plural pieces of meta data, and
control the memory device to store the plural pieces of meta data and the additional meta data in the first region and the second region, respectively,
wherein the second region includes:
an additional meta data storage region of which a size is determined based on the additional meta data corresponding to the plural pieces of meta data; and
a head region configured to store size information which is associated with the additional meta data, and
wherein the memory controller controls the memory device to store the additional meta data in the additional meta data storage region.
2. The memory system of claim 1 , wherein the meta page is included in a meta data block among the plurality of memory blocks.
3. The memory system of claim 2 , wherein memory cells included in the meta data block are configured with a Single Level Cell (SLC).
4. The memory system of claim 1 , wherein the head region is further configured to store address information and effective information which are associated with the additional meta data.
5. The memory system of claim 4 , wherein the size information indicates a size of the additional meta data storage region, and
wherein the address information includes at least one of a start address and an end address of a region in which the additional meta data are stored.
6. The memory system of claim 1 , wherein a size of the head region is constant.
7. The memory system of claim 1 ,
wherein the head region is allocated in a direction toward a lowest address from a highest address among physical addresses corresponding to the meta page, and
wherein the additional meta data storage region is allocated in a direction toward a lowest address of the meta page from a lowest address of the head region.
8. The memory system of claim 1 ,
wherein the first region includes a plurality of meta data storage regions classified according to the types of the plural pieces of meta data, and
wherein other meta data storage regions except a meta data storage region adjacent to the second region among the plurality of meta data storage regions have a fixed size.
9. The memory system of claim 8 , wherein sizes of the plurality of meta data storage regions are different from each other according to the types of the plural pieces of meta data.
10. The memory system of claim 1 , wherein the first region is allocated in a direction towards a highest address from a lowest address among physical addresses corresponding to the meta page.
11. The memory system of claim 1 , wherein the plural pieces of meta data include at least one of a read count, an erase count, map data, and a meta data log.
12. A memory system comprising:
a nonvolatile memory device including a meta page;
a read buffer configured to temporarily store plural pieces of meta data stored in the meta page;
a plurality of meta data storages configured to classify and store the plural pieces of meta data stored in the read buffer according to types of the plural pieces of meta data; and
a memory controller configured to control the nonvolatile memory device, the read buffer, and the plurality of meta data storages,
wherein the meta page includes:
a dedicated region configured to classify and store the plural pieces of meta data according to the types of the meta data; and
a common region configured to store additional meta data corresponding to the plural pieces of meta data stored in the dedicated region,
wherein the common region includes:
an additional meta data storage region configured to store the additional meta data corresponding to the plural pieces of meta data; and
a head region configured to store information which is associated with the additional meta data, and
wherein the memory controller is further configured to:
store, in the plurality of meta data storages, the plural pieces of meta data stored in the dedicated region of the meta page,
store the additional meta data stored in the common region of the meta page in meta data storages which are determined based on the information stored in the head region among the plurality of meta data storages, and
update the meta page based on the plural pieces of meta data stored in the plurality of meta data storages.
13. The memory system of claim 12 , wherein the information associated with the additional meta data includes size information, address information, and effective information on the additional meta data.
14. The memory system of claim 13 , wherein the memory controller is configured to update firmware based on the plural pieces of meta data stored in the plurality of meta data storages.
15. The memory system of claim 12 ,
wherein the dedicated region is allocated in a direction towards a highest address from a lowest address among physical addresses corresponding to the meta page, and
wherein the common region is allocated in a direction towards the lowest address from the highest address among the physical addresses corresponding to the meta page.
16. A method of operating a memory controller, the method comprising:
reading data stored in a meta page in a first memory device, the meta page including a dedicated region configured to store plural pieces of meta data and a common region configured to store additional meta data corresponding to the plural pieces of meta data, the common region including a head region configured to store information associated with the additional meta data and an additional meta data storage region;
storing the plural pieces of meta data stored in the dedicated region respectively in allocated regions, according to types of the plural pieces of meta data; and
storing the additional meta data stored in the additional meta data storage region included in the common region in the allocated regions which are determined based on the information stored in the head region, according to the types of the plural pieces of meta data.
17. The method of claim 16 , wherein the plural pieces of meta data include at least one of map data, a meta data log, a read count, and an erase count.
18. The method of claim 16 ,
wherein the information associated with the additional meta data includes size information, address information, and effective information on the additional meta data, and
wherein the head region is allocated in a direction towards a lowest address from a highest address among physical addresses corresponding to the meta page.
19. The method of claim 16 , wherein the storing of the additional meta data stored in the common region includes:
calculating a size of the common region, based on size information stored in the head region;
calculating a size of the additional meta data, based on address information stored in the head region; and
storing effective additional meta data in the allocated regions according to types of the effective additional meta data, based on effective information stored in the head region.