IP Library › Granted Patent US 12,455,996
Granted Patent B2
US 12,455,996 · App. 18/482,749 · Granted Oct 28, 2025

Remedial action in an integrated circuit in response to a monitor circuit diagnostic code sequence

Inventors: Anatoly Gelman (San Diego, CA); Michael James Smith (Vancouver, CA); James Cheng-Huan Wu (Vancouver, CA); Olivier Alavoine (San Diego, CA); Amit Aneja (Chandler, AZ)
Assignee: Qualcomm Incorporated
G06F30/343G01R31/318566G06F1/3228G06F1/3296G06F11/27G06F30/327G06F2119/06G06F2119/12
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Quick Facts
Patent No.
US 12,455,996
App. No.
18/482,749
Granted
Oct 28, 2025
Kind
B2
Abstract

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

Claims (36)

1 . An apparatus comprising:

an integrated circuit having a logic path formed in the integrated circuit;

a monitor circuit formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time;

a log to store the diagnostic code sequence; and

a monitor controller configured to receive diagnostic codes of the diagnostic code sequence, to store the diagnostic codes in the log with a corresponding time stamp, to determine a condition of the integrated circuit based on the diagnostic code sequence that is stored in the log, and to initiate a remedial action in response to the condition of the integrated circuit.

2 . The apparatus of claim 1 , wherein the remedial action comprises modifying a power supply voltage to the logic path in response to the condition of the logic path.

3 . The apparatus of claim 2 , comprising a power management circuit coupled to the integrated circuit and wherein the monitor controller is configured to modify the power supply voltage by sending a command to the power management circuit.

4 . The apparatus of claim 2 , wherein the monitor controller is configured to determine a timing margin of the integrated circuit and to increase the power supply voltage to increase the timing margin.

5 . The apparatus of claim 4 , wherein the monitor controller is configured to determine that the power supply voltage cannot be increased more and to declare a maintenance event in response thereto.

6 . The apparatus of claim 2 , wherein the monitor controller is configured to determine that a maximum number of aging compensation steps have been taken and to declare a maintenance event in response thereto.

7 . The apparatus of claim 6 , wherein the monitor controller is coupled to a maintenance facility to send the maintenance event to the maintenance facility.

8 . The apparatus of claim 2 , wherein the monitor controller is configured to set a flag in a configuration register of a power management circuit to cause the power management circuit to modify the power supply voltage after the integrated circuit is restarted.

9 . The apparatus of claim 2 , wherein the monitor controller is configured to store a flag in a log of the monitor controller to modify the power supply voltage after an integrated circuit restart.

10 . The apparatus of claim 2 , wherein the monitor controller is configured to set a flag in a configuration register to trigger a test of the logic path upon a restart of the integrated circuit.

11 . The apparatus of claim 1 , wherein the monitor controller is configured to initiate a shutdown of at least a portion of the integrated circuit that includes the logic path in response to the condition of the integrated circuit.

12 . The apparatus of claim 1 , comprising a second monitor circuit formed in the integrated circuit and configured to generate a second diagnostic code to indicate the condition of the logic path and wherein the monitor controller is configured to aggregate the first diagnostic code and the second diagnostic code.

13 . The apparatus of claim 1 , further comprising

an external data port coupled to an external safety management control unit,

wherein the monitor controller is configured to send functional safety messages to the external safety management control unit through the external data port in response to the condition of the integrated circuit.

14 . A method comprising:

monitoring a condition of a logic path formed in an integrated circuit at a monitor circuit formed in the integrated circuit near the logic path;

generating a diagnostic code sequence to indicate the condition of the logic path over time;

storing the diagnostic code sequence in a log with a corresponding time stamp; and

determining a condition of the integrated circuit based on the diagnostic code sequence that is stored in the log; and

initiating a remedial action in response to the condition of the integrated circuit.

15 . The method of claim 14 , wherein initiating a remedial action comprises modifying the power supply voltage by sending a command to a power management circuit.

16 . The method of claim 15 , further comprising determining that a maximum number of aging compensation steps have been taken and declaring a maintenance event in response thereto.

17 . The method of claim 15 , further comprising determining a timing margin of the integrated circuit and wherein initiating a remedial action comprises increasing a power supply voltage to increase the timing margin.

18 . The method of claim 17 , further comprising determining that the power supply voltage cannot be increased more and declaring a maintenance event in response thereto.

19 . A non-transitory computer-readable medium having instructions that when executed by the machine cause the machine to perform operations including:

monitoring a condition of a logic path formed in an integrated circuit at a monitor circuit formed in the integrated circuit near the logic path;

generating a diagnostic code sequence to indicate the condition of the logic path over time;

storing the diagnostic code sequence in a log with a corresponding time stamp;

determining a condition of the integrated circuit based on the diagnostic code sequence that is stored in the log; and

initiating a remedial action in response to the condition of the integrated circuit.

20 . The medium of claim 19 , the operations further comprising initiating a shutdown of at least a portion of the integrated circuit that includes the logic path in response to the condition of the integrated circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2023
From: GELMAN, ANATOLY; SMITH, MICHAEL JAMES; WU, JAMES CHENG-HUAN; ALAVOINE, OLIVIER; ANEJA, AMIT
To: QUALCOMM INCORPORATED
Reel/Frame 065607/0560 →
Continuity (2)
Provisional Application 63514774 · Jul 20, 2023
Related Publication 20250028377A1 · Jan 23, 2025
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Cited By (1)
US 12,688,349