Method of fabricating thin, crystalline silicon film and thin film transistors
A method of producing a reduced-defect density crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, forming a silicon film on the Six2Ge1-x2 film, and annealing to crystallize the Six1Ge1-x1, Six2Ge1-x2, and silicon films. The values of x1 and x2 are between zero and one. The Six1Ge1-x1 and Six2Ge1-x2 films are amorphous at formation, having a first thermal budget and a second thermal budget, respectively, for crystallization, the second thermal budget lower than the first thermal budget, the Six2Ge1-x2 film spaced apart from the substrate by the Six1Ge1-x1 film. A crystalline silicon TFT device includes a substrate, a crystallized Six1Ge1-x1 layer on the substrate, a crystallized Six2Ge1-x2 layer on the crystallized Six1Ge1-x1 layer, a crystallized silicon layer on the Six2Ge1-x2 layer, a gate insulator layer on the crystallized silicon layer, and a gate electrode on the gate insulator layer.
1. A method of producing a reduced-defect density crystalline silicon film, comprising:
forming a Si x1 Ge 1-x1 film on a substrate, x1 having a value between zero and one not including zero, the Si x1 Ge 1-x1 film being amorphous at formation and having a first thermal budget for crystallization;
forming a Si x2 Ge 1-x2 film on the Si x1 Ge 1-x1 film, x2 having a value between zero and one including zero, the value of x2 being smaller than the value of x1, the Si x2 Ge 1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, the Si x2 Ge 1-x2 film being spaced apart from the substrate by the Si x1 Ge 1-x1 film;
forming a silicon film on the Si x2 Ge 1-x2 film, the silicon film being amorphous at formation; and
annealing to crystallize the Si x1 Ge 1-x1 film, the Si x2 Ge 1-x2 film, and the silicon film, such that crystallization is initiated within the Si x2 Ge 1-x2 film and propagates through the silicon film and the Si x1 Ge 1-x1 film, transforming the silicon film to a reduced-density, crystallized silicon film.
2. The method of claim 1 further comprising forming a doped silicon film between the Si x2 Ge 1-x2 film and the silicon film, wherein the doped silicon film is amorphous at formation, wherein the annealing is performed to crystallize the Si x2 Ge 1-x2 film, the Si x1 Ge 1-x1 film, the doped silicon film, and the silicon film, such that the crystallization is initiated within the Si x2 Ge 1-x2 film, and the crystallization propagates through the doped silicon film, the silicon film, and the Si x1 Ge 1-x1 film.
3. The method of claim 2 , wherein forming the doped silicon film between the Si x2 Ge 1-x2 film and the silicon film includes forming the doped silicon film in direct contact with the silicon film, the method further comprising the steps:
doping the silicon film in selected areas to form source and drain regions separated by a channel portion, such that a conductivity type of the source and drain regions is opposite the conductivity type of the doped silicon film;
forming a gate insulator film on the silicon film; and
forming a gate electrode pattern over the gate insulator film.
4. The method of claim 1 , wherein the Si x2 Ge 1-x2 film is doped.
5. The method of claim 1 , wherein the Si x2 Ge 1-x2 film has a Ge fraction and the Si x1 Ge 1-x1 film has a Ge fraction, the Ge fraction of the Si x2 Ge 1-x2 film being higher than the Ge fraction of the Si x1 Ge 1-x1 film.
6. The method of claim 1 wherein the Si x2 Ge 1-x2 film has a doping concentration and the Si x1 Ge 1-x1 film has a doping concentration, the doping concentration of the Si x2 Ge 1-x2 film being higher than the doping concentration of the Si x1 Ge 1-x1 film.
7. The method of claim 1 wherein the annealing temperature is 600 degrees Celsius or lower.
8. The method of claim 1 , wherein the annealing has a thermal budget lower than a thermal budget required to crystallize the Si x1 Ge 1-x1 film and the silicon film without the presence of the Si x2 Ge 1-x2 film between the Si x1 Ge 1-x1 film and the silicon film.
9. The method of claim 1 , wherein forming the silicon film on the Si x2 Ge 1-x2 film includes forming the silicon film in direct contact with the Si x2 Ge 1-x2 film, the method further comprising the steps:
doping the silicon film in selected areas to form source and drain regions separated by a channel portion, such that a conductivity type of the source and drain regions is opposite the conductivity type of the Si x2 Ge 1-x2 film;
forming a gate insulator film on the silicon film; and
forming a gate electrode pattern over the gate insulator film.
10. The method of claim 1 , wherein the Si x1 Ge 1-x1 film has a thickness in a range of 500 to 1500 angstrom, the Si x2 Ge 1-x2 film has a thickness in a range of 500-1000 angstrom, and the silicon film has a thickness in a range of 200-1000 angstrom.
11. A method of producing a reduced-defect density crystalline silicon film, comprising:
forming a first Si x Ge 1-x film on a substrate, where x has a value between zero and one, including zero, the Si x Ge 1-x film being amorphous at formation and having a first thermal budget for crystallization;
forming a second Si x Ge 1-x film on the first Si x Ge 1-x film, the second Si x Ge 1-x film being doped, the second Si x Ge 1-x film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, the second Si x Ge 1-x film being spaced from the substrate by the first Si x Ge 1-x film;
forming a silicon film on the second Si x Ge 1-x film, the silicon film being amorphous at formation; and
annealing to crystallize the first Si x Ge 1-x film, the second Si x Ge 1-x film, and the silicon film, such that crystallization is initiated within the second Si x Ge 1-x film and propagates through the silicon film and the first Si x1 Ge 1-x1 film, transforming the silicon film to a reduced-density, crystallized silicon film.
12. The method of claim 11 , further comprising forming a doped silicon film between the second Si x Ge 1-x film and the silicon film, wherein the doped silicon film is amorphous at formation, wherein the annealing is performed to crystallize the second Si x Ge 1-x film, the first Si x Ge 1-x film, the doped silicon film, and the silicon film, such that the crystallization is initiated within the second Si x Ge 1-x film, and the crystallization propagates through the doped silicon film, the silicon film, and the first Si x Ge 1-x film.
13. The method of claim 12 , wherein forming the doped silicon film between the second Si x Ge 1-x film and the silicon film includes forming the doped silicon film in direct contact with the silicon film, the method further comprising the steps:
doping the silicon film in selected areas to form source and drain regions separated by a channel portion, such that a conductivity type of the source and drain regions is opposite the conductivity type of the doped silicon film;
forming a gate insulator film on the silicon film; and
forming a gate electrode pattern over the gate insulator film.
14. The method of claim 11 , wherein the second Si x Ge 1-x film has a doping concentration and the first Si x Ge 1-x film has a doping concentration, the doping concentration of the second Si x Ge 1-x film being higher than the doping concentration of the first Si x Ge 1-x film.
15. The method of claim 11 , wherein the annealing temperature is 600 degrees Celsius or lower.
16. The method of claim 11 , wherein the annealing has a thermal budget lower than a thermal budget required to crystallize the first Si x Ge 1-x film and the silicon film without the presence of the second Si x Ge 1-x film between the first Si x Ge 1-x film and the silicon film.
17. The method of claim 11 , wherein forming the silicon film on the second Si x Ge 1-x film includes forming the silicon film in direct contact with the second Si x Ge 1-x film, the method further comprising the steps:
doping the silicon film in selected areas to form source and drain regions separated by a channel portion, such that a conductivity type of the source and drain regions is opposite the conductivity type of the second Si x Ge 1-x film;
forming a gate insulator film on the silicon film; and
forming a gate electrode pattern over the gate insulator film.
18. The method of claim 11 , wherein the first Si x Ge 1-x film has a thickness in a range of 500 to 1500 angstrom, the second Si x Ge 1-x film has a thickness in a range of 500-1000 angstrom, and the silicon film has a thickness in a range of 200-1000 angstrom.