Method for manufacturing semiconductor device having buried gate structure
The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a trench in a substrate and disposing a lower gate electrode in the trench. The method also includes disposing a first dielectric layer on the lower gate electrode in the trench and partially removing the first dielectric layer to expose a portion of the lower gate electrode.
1. A method of manufacturing a semiconductor device, comprising:
forming a trench in a substrate;
disposing a lower gate electrode in the trench;
disposing a first dielectric layer on the lower gate electrode in the trench;
partially removing the first dielectric layer to expose a portion of the lower gate electrode, wherein a remained first dielectric layer covers another portion of the lower gate electrode;
disposing a first barrier layer on the portion of the lower gate electrode; and
forming a coplanar surface of the first barrier layer and the first dielectric layer.
2. The method of claim 1 , further comprising:
partially removing the first dielectric layer and the first barrier layer.
3. The method of claim 2 , further comprising:
before disposing the lower gate electrode, forming a second dielectric layer in the trench.
4. The method of claim 3 , wherein the second dielectric layer is protected by the first dielectric layer when the first dielectric layer and the first barrier layer are removed.
5. The method of claim 1 , further comprising:
before disposing the lower gate electrode, forming a second barrier layer in the trench.
6. The method of claim 1 , further comprising:
disposing an upper gate electrode on the first dielectric layer.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate having a trench; and
forming a gate structure in the trench, comprising:
forming a lower gate electrode;
forming an upper gate electrode over the lower gate electrode;
forming a first barrier layer between the lower gate electrode and the upper gate electrode; and
forming a first dielectric layer between the lower gate electrode and the upper gate electrode;
wherein the first dielectric layer is adjacent to the first barrier layer, the first dielectric layer partially covers the lower gate electrode;
wherein an upper surface of the first barrier layer and an upper surface of the first dielectric layer are substantially coplanar.
8. The method of claim 7 , wherein the first barrier layer contacts the lower gate electrode and the upper gate electrode.
9. The method of claim 8 , wherein the first dielectric layer contacts the lower gate electrode and the upper gate electrode.
10. The method of claim 7 , wherein the first barrier layer and the first dielectric layer comprise different nitrides.
11. The method of claim 7 , further comprising:
forming a second dielectric layer between the lower gate electrode and the substrate.
12. The method of claim 11 , wherein the first barrier layer is spaced apart from the second dielectric layer by the first dielectric layer.
13. The method of claim 11 , wherein the second dielectric layer comprises a sidewall between the upper gate electrode and the substrate.
14. The method of claim 7 , wherein the sidewall of the second dielectric layer is substantially perpendicular to an upper surface of the first barrier layer.
15. The method of claim 7 , wherein the first dielectric layer comprises a curved surface, and wherein the curved surface of the first dielectric layer is covered by the first barrier layer.
16. The method of claim 7 , further comprising:
forming a second barrier layer between the lower gate electrode and the substrate;
wherein second barrier layer contacts the first dielectric layer.
17. A method of manufacturing a semiconductor device, comprising:
providing a substrate having a trench; and
forming a gate structure in the trench, comprising:
forming a lower gate electrode;
forming an upper gate electrode over the lower gate electrode;
forming a first barrier layer between the lower gate electrode and the upper gate electrode; and
forming a first dielectric layer between the lower gate electrode and the upper gate electrode;
wherein the first dielectric layer is adjacent to the first barrier layer, the first dielectric layer partially covers the lower gate electrode;
wherein a lower surface of the first barrier layer and a lower surface of the first dielectric layer are substantially coplanar.