IP Library Granted Patent US 12,457,733
Granted Patent B2
US 12,457,733 · App. 17/896,933 · Granted Oct 28, 2025

Semiconductor device having bonding structure and method of manufacturing the same

Inventors: Yi-Jen Lo (New Taipei, TW); Chiang-Lin Shih (New Taipei, TW); Hsih-Yang Chiu (Taoyuan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H10B12/315H01L23/5283H01L23/53295H10B12/0335H10B12/482H10B12/488
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Quick Facts
Patent No.
US 12,457,733
App. No.
17/896,933
Granted
Oct 28, 2025
Kind
B2
Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.

Claims (24)

1. A semiconductor device, comprising:

a substrate;

a bonding structure disposed on the substrate;

a bit line disposed on the bonding structure;

a channel layer disposed on the bit line, and comprising a first doped region and a second doped region; and

a word line surrounding the first doped region and the second doped region of the channel layer,

wherein the bonding structure comprises a dielectric material, and

wherein the first doped region has a first conductive type, and the second doped region has a second conductive type different from the first type.

2. The semiconductor device of claim 1 , wherein the first doped region is adjacent to the bit line and a second doped region is formed on the first doped region.

3. The semiconductor device of claim 2 , wherein a portion of the first doped region of the channel layer is exposed by the word line.

4. The semiconductor device of claim 2 , wherein the second doped region of the channel layer is completely covered by the word line.

5. The semiconductor device of claim 2 , wherein the channel layer comprises a third doped region having the first conductive type, and the second doped region is disposed between the first doped region and the third doped region.

6. The semiconductor device of claim 5 , wherein a portion of the third doped region of the channel layer is exposed by the word line.

7. The semiconductor device of claim 1 , further comprising:

a conductive feature disposed between the substrate and the bonding structure.

8. The semiconductor device of claim 7 , further comprising:

a conductive plug penetrating the dielectric structure and electrically connected to the conductive feature.

9. The semiconductor device of claim 8 , wherein the conductive plug has a first aperture and a second aperture different from the first aperture.

10. The semiconductor device of claim 8 , wherein the contact plug has a first portion with a first height and a second portion with a second height different from the first height.

11. The semiconductor device of claim 10 , wherein the first portion of the contact plug is spaced apart from the conductive feature by the dielectric structure.

12. The semiconductor device of claim 11 , wherein the second portion of the contact plug penetrates the dielectric structure.

13. The semiconductor device of claim 7 , wherein the bit line is spaced apart from the conductive feature by the dielectric structure.

14. The semiconductor device of claim 1 , wherein the bonding structure comprises a first dielectric layer and a second dielectric layer.

15. The semiconductor device of claim 14 , wherein the bonding structure comprises a plurality of voids located at an interface between the first dielectric layer and the second dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2022
From: LO, YI-JEN; SHIH, CHIANG-LIN; CHIU, HSIH-YANG
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 061094/0656 →
Continuity (1)
Related Publication 20240074145A1 · Feb 29, 2024
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