Thermal isolation between embedded MECA modules
An electronic assembly, having a carrier wafer with a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising first and second integrated circuit contact pads; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; first and second component chips held in said through-wafer cavity each by direct contact of at least a side surface of said first and second component chips with a heat conducting attachment material that fills said through-wafer cavity; said first and second component chips comprising respectively at least a first and a second component contact pads; a barrier having a heat conductivity lower than a heat conductivity of said carrier wafer held by said heat conducting attachment material in said through-wafer cavity between said first and said second component chips.
1 . An electronic assembly, having:
a carrier wafer with a top wafer surface and a bottom wafer surface;
an electronic integrated circuit being formed in the carrier wafer and comprising first and second integrated circuit contact pads on at least one of the top wafer surface and the bottom wafer surface; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface;
a first component chip with a first component chip top surface, a first component chip bottom surface and first component chip side surfaces, the first component chip being held in said through-wafer cavity by direct contact of at least a side surface of said first component chip with a heat conducting attachment material that fills at least a portion of said through-wafer cavity; said first component chip comprising at least one first component contact pad on at least one of said first component chip top surface and said first component chip bottom surface;
a second component chip with a second component chip top surface, a second component chip bottom surface and second component chip side surfaces, the second component chip being held in said through-wafer cavity by direct contact of at least a side surface of said second component chip with said heat conducting attachment material; said second component chip comprising at least one second component contact pad on at least one of said second component chip top surface and said second component chip bottom surface;
wherein a barrier having a heat conductivity lower than a heat conductivity of said carrier wafer is held by said heat conducting attachment material in said through-wafer cavity between said first and said second component chips;
and having at least one of:
a first conductor connecting said first integrated circuit contact pad and said first component contact pad; and
a second conductor connecting said second integrated circuit contact pad and said second component contact pad;
wherein said heat conducting attachment material is a metal.
2 . The assembly of claim 1 , wherein, the first and second component chips have first and second heights and the barrier has a barrier height at least as large as the smallest of the first and second heights.
3 . The assembly of claim 1 , wherein, the through-wafer cavity has a cavity height and the barrier height is equal to the cavity height.
4 . The assembly of claim 1 , wherein the first and second component chips have each a side closest to the barrier that have first and second lengths, and wherein the barrier has a barrier length at least as large as the smallest of said first and second lengths.
5 . The assembly of claim 1 , wherein, the through-wafer cavity has a cavity length and the barrier length is equal to the cavity length.
6 . The assembly of claim 1 , wherein the barrier comprises two walls arranged each parallel to a different side surface of one of the first and second component chips.
7 . The assembly of claim 1 , wherein the barrier surrounds one of the first and second component chips.
8 . The assembly of claim 1 , wherein the barrier material comprises one of air, ceramic and glass.
9 . The assembly of claim 1 , wherein the barrier has a thickness equal to one fifth or more of a distance between the first and second component chips.
10 . The assembly of claim 1 , wherein the heat conducting attachment material holds the first and second component chips such that the first and second component chips top surfaces are flush with the top wafer surface.
11 . The assembly of claim 1 , wherein a metal layer covers at least a portion of the bottom wafer surface as well as the heat conducting attachment material in the through-wafer cavity.
12 . The assembly of claim 1 , wherein the walls of the through-wafer cavity are covered with a dielectric layer.
13 . The assembly of claim 1 , wherein the heat-conducting attachment material contacts more than half of each first and second component chips side surfaces.
14 . The assembly of claim 1 , wherein the carrier wafer and at least the first or second component chips are made of different materials.
15 . The assembly of claim 1 , wherein at least one of the first and second component chips is an integrated circuit chip comprising one or more transistors.
16 . The assembly of claim 1 , wherein the carrier wafer and at least one of the first and second component chips have a different height.
17 . A method of manufacturing an electronic assembly, the method comprising:
providing a first component chip having a first component chip top surface, a first component chip bottom surface and first component chip side surfaces; said first component chip comprising at least one first component contact pad on said first component chip top surface;
providing a second component chip having a second component chip top surface, a second component chip bottom surface and second component chip side surfaces; said second component chip comprising at least one second component contact pad on said second component chip top surface;
providing a handle wafer having a first surface, and attaching said first and second component chips top surfaces to said first surface of said handle wafer;
providing a carrier wafer having a top wafer surface and a bottom wafer surface; forming in the carrier wafer an electronic integrated circuit having first and second integrated circuit contact pads on the top wafer surface; forming in the carrier wafer a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface;
attaching said top wafer surface to said first surface of said handle wafer such that said first and second component chips are arranged within said through-wafer cavity;
positioning a barrier structure having a heat conductivity lower than a heat conductivity of said carrier wafer in said through-wafer cavity between the first and second component chips;
filling at least a portion of said through-wafer cavity with a heat conducting attachment material so as to hold the first and second component chips in said through-wafer cavity by direct contact of at least a side surface of said first and second component chips with said heat conducting attachment material and so as to hold said barrier structure between the first and second component chips by direct contact with said heat conducting attachment material;
detaching the handle wafer from the first and second component chips top surface and the top wafer surface; and
at least one of:
forming a first conductor between the first integrated circuit contact pad and said first component contact pad; and
forming a second conductor between the second integrated circuit contact pad and said second component contact pad;
wherein said heat conducting attachment material is a metal.
18 . The method of claim 17 , wherein said positioning a barrier structure having a heat conductivity lower than a heat conductivity of said carrier wafer in said through-wafer cavity between the first and second component chips comprises attaching the barrier structure to said first surface of said handle wafer and/or to at least a wall of said through-wafer cavity.
19 . The method of claim 17 , wherein said filling at least a portion of said through-wafer cavity with said metal comprises depositing said metal by electroplating.
20 . The method of claim 17 , wherein the barrier structure comprises two walls arranged each parallel to a different side surface of one of the first and second component chips.
21 . The method of claim 17 , wherein the barrier structure is arranged parallel to at least two side surfaces of one of the first and second component chips.
22 . The method of claim 17 , wherein the barrier structure surrounds one of the first and second component chips.
23 . The method of claim 17 , wherein said positioning a barrier structure between the first and second component chips comprises positioning a sacrificial structure between the first and second component chips which can be removed, after said filling at least a portion of said through-wafer cavity with an attachment material, to provide a barrier structure made out of air.