Device and method for fabricating double-sided SOI wafer scale package with optical through via connections
View Patent ↗A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system.
1. A method for forming a semiconductor package, comprising the steps of:
forming an optical through via through a first side of a wafer;
forming a cavity on a second side of the wafer exposing a portion of the optical through via; and
placing at least one sub-chip in the cavity and optically coupling the sub-chip to the optical through via.
2. The method as recited in claim 1 , wherein the wafer includes a silicon-on-insulator wafer and forming an optical through via through a first side of a wafer includes etching a via hole through a top silicon layer and a buried dielectric layer and filling the via hole with an optical material.
3. The method as recited in claim 1 , wherein the step of forming a cavity on a second side of the wafer exposing a portion of the through via includes etching a silicon substrate of the wafer to expose the portion of the optical through via.
4. The method as recited in claim 1 , wherein placing at least one sub-chip in the cavity and optically coupling the sub-chip to the optical through via includes aligning the optical through via with an optical link in the sub-chip to permit optical communications therebetween.
5. The method as recited in claim 1 , wherein connecting the sub-chip to the optical through via includes employing optical and electrical connections.
6. The method as recited in claim 1 , further comprising providing optical and electrical connections between the wafer and an external device.
7. The method as recited in claim 1 , further comprising optically connecting a device on the wafer with the subchip through the optical through via to provide optical communication therebetween.
8. A method for forming a semiconductor package, comprising the steps of:
forming an optical through via through a first side of a wafer;
forming a cavity on a second side of the wafer exposing a portion of the optical through via;
placing at least one sub-chip in the cavity and optically coupling the sub-chip to the optical through via to permit optical signal communication through the optical through via; and
connecting the sub-chip to the wafer using electrical connections.
9. The method as recited in claim 8 , wherein the wafer includes a silicon-on-insulator wafer and forming an optical through via through a first side of a wafer includes etching a via hole through a top silicon layer and a buried dielectric layer and filling the via hole with an optical material.
10. The method as recited in claim 8 , wherein the step of forming a cavity on a second side of the wafer exposing a portion of the through via includes etching a silicon substrate of the wafer to expose the portion of the optical through via.
11. The method as recited in claim 8 , wherein placing at least one sub-chip in the cavity and optically coupling the sub-chip to the optical through via includes aligning the optical through via with an optical link in the sub-chip to permit optical communications therebetween.
12. The method as recited in claim 8 , further comprising providing optical and electrical connections between the wafer and an external device.
13. The method as recited in claim 8 , further comprising optically communicating between the wafer and the subchip through the optical through via.