IP Library Granted Patent US 12,464,746
Granted Patent B1
US 12,464,746 · App. 18/945,645 · Granted Nov 4, 2025

Isolation stack for a bipolar transistor and related methods

Inventors: Jacob M. DeAngelis (Essex Junction, VT); Uppili S. Raghunathan (Essex Junction, VT); Steven M. Shank (Jericho, VT); Sarah A. McTaggart (Essex Junction, VT); Megan Elizabeth Lydon-Nuhfer (Essex Junction, VT); Cameron Luce (Colchester, VT)
Assignee: GlobalFoundries U.S. Inc.
H10D10/821H10D10/021H10D62/115H10D62/133H10D62/137H10D62/177
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,464,746
App. No.
18/945,645
Granted
Nov 4, 2025
Kind
B1
Abstract

The disclosure provides an isolation stack for a bipolar transistor (BT), and related methods. A structure of the disclosure includes a first isolation layer on a subcollector. A first air gap is between the first isolation layer and a collector of a BT. A second isolation layer is on the first isolation layer and adjacent an intrinsic base of the BT. A third isolation layer is on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT. A second air gap is adjacent the third isolation layer and below the extrinsic base.

Claims (28)

1 . A structure comprising:

a first isolation layer on a subcollector, wherein a first air gap is between the first isolation layer and a collector of a bipolar transistor (BT);

a second isolation layer on the first isolation layer and adjacent an intrinsic base of the BT; and

a third isolation layer on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT, wherein a second air gap is adjacent the third isolation layer and below the extrinsic base, and wherein the second isolation layer defines a physical boundary between the first air gap and the second air gap.

2 . The structure of claim 1 , wherein the second isolation layer is adjacent a lower portion of the intrinsic base of the BT, and wherein the second air gap is adjacent an upper portion of the intrinsic base of the BT.

3 . The structure of claim 1 , wherein the first isolation layer and the third isolation layer each include a same material.

4 . The structure of claim 1 , wherein the first isolation layer, the second isolation layer, and the third isolation layer form an oxide-nitride-oxide (ONO) stack.

5 . The structure of claim 1 , wherein the first air gap is one of a pair of first air gaps each adjacent a sidewall of the collector, and wherein the second air gap is one of a pair of second air gaps each adjacent a sidewall of the intrinsic base.

6 . The structure of claim 1 , wherein the BT is a vertically-oriented heterojunction bipolar transistor.

7 . A structure comprising:

a bipolar transistor (BT) including a subcollector, a collector on the subcollector, an intrinsic base on the collector, an extrinsic base on a first portion of the intrinsic base, and an emitter on a second portion of the intrinsic base; and

an isolation stack adjacent the BT, the isolation stack including:

a first isolation layer on the subcollector, wherein a first air gap is between the first isolation layer and the collector, and wherein a portion of the first air gap is above a portion of the collector;

a second isolation layer on the first isolation layer and adjacent the intrinsic base of the BT; and

a third isolation layer on the second isolation layer, vertically between the second isolation layer and the extrinsic base of the BT, wherein a second air gap is adjacent the third isolation layer and below the extrinsic base, wherein the second isolation layer defines a physical boundary between the first air gap and the second air gap.

8 . The structure of claim 7 , wherein the second isolation layer of the isolation stack is adjacent a lower portion of the intrinsic base of the BT, and wherein the second air gap is adjacent an upper portion of the intrinsic base of the BT.

9 . The structure of claim 7 , wherein the first isolation layer and the third isolation layer each include a same material.

10 . The structure of claim 7 , wherein the first isolation layer, the second isolation layer, and the third isolation layer form an oxide-nitride-oxide (ONO) stack.

11 . The structure of claim 7 , wherein the emitter of the BT is one of a plurality of emitters on the second portion of the intrinsic base.

12 . A method comprising:

forming a first isolation layer on a subcollector, wherein a first air gap is between the first isolation layer and a collector of a bipolar transistor (BT);

forming a second isolation layer on the first isolation layer and adjacent an intrinsic base of the BT; and

forming a third isolation layer on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT, wherein a second air gap is adjacent the third isolation layer and below the extrinsic base, wherein forming the second isolation layer defines a physical boundary between the first air gap and the second air gap.

13 . The method of claim 12 , wherein the second isolation layer is adjacent a lower portion of the intrinsic base of the BT, and wherein the second air gap is adjacent an upper portion of the intrinsic base of the BT.

14 . The method of claim 12 , wherein the first isolation layer and the third isolation layer each include a same material.

15 . The method of claim 12 , wherein forming the first isolation layer, the second isolation layer, and the third isolation layer includes forming an oxide-nitride-oxide (ONO) stack.

16 . The method of claim 12 , wherein the first air gap is one of a pair of first air gaps each adjacent a sidewall of the collector, and wherein the second air gap is one of a pair of second air gaps each adjacent a sidewall of the intrinsic base.

17 . The method of claim 12 , further comprising forming the BT as a vertically-oriented heterojunction bipolar transistor on the subcollector.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2024
From: DEANGELIS, JACOB M.; RAGHUNATHAN, UPPILI S.; SHANK, STEVEN M.; MCTAGGART, SARAH A.; LYDON-NUHFER, MEGAN ELIZABETH; LUCE, CAMERON
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 069243/0734 →
References Cited (81)
US 5516710A · Boyd et al. · 1996 [cited by applicant]
US 6869852B1 · Joseph et al. · 2005 [cited by applicant]
US 6940149B1 · Divakaruni · 2005 [cited by examiner]
US 6964907B1 · Hopper · 2005 [cited by examiner]
US 7214593B2 · Coolbaugh et al. · 2007 [cited by applicant]
US 7462923B1 · U'Ren · 2008 [cited by applicant]
US 7709338B2 · Liu et al. · 2010 [cited by applicant]
US 7750371B2 · Gluschenkov et al. · 2010 [cited by applicant]
US 7846805B2 · Zhang et al. · 2010 [cited by applicant]
US 7883954B2 · Magnee et al. · 2011 [cited by applicant]
US 7952165B2 · Cohen et al. · 2011 [cited by applicant]
US 8067290B2 · Boeck et al. · 2011 [cited by applicant]
US 8395217B1 · Cheng et al. · 2013 [cited by applicant]
US 8405127B2 · Chu et al. · 2013 [cited by applicant]
US 8558282B1 · Cai et al. · 2013 [cited by applicant]
US 8853043B2 · Hodge et al. · 2014 [cited by applicant]
US 9029229B2 · Adkisson et al. · 2015 [cited by applicant]
US 9070734B2 · Camillo-Castillo et al. · 2015 [cited by applicant]
US 9093491B2 · Adkisson et al. · 2015 [cited by applicant]
US 9159817B2 · Camillo-Castillo et al. · 2015 [cited by applicant]
US 9202900B2 · Adkisson et al. · 2015 [cited by applicant]
US 9240448B2 · Adkisson et al. · 2016 [cited by applicant]
US 9245951B1 · Camillo-Castillo et al. · 2016 [cited by applicant]
US 9318551B2 · Camillo-Castillo et al. · 2016 [cited by applicant]
US 9368608B1 · Camillo-Castillo et al. · 2016 [cited by applicant]
US 9508824B2 · Fox et al. · 2016 [cited by applicant]
US 9570564B2 · Alperstein et al. · 2017 [cited by applicant]
US 9583569B2 · Camillo-Castillo et al. · 2017 [cited by applicant]
US 9653566B2 · Camillo-Castillo et al. · 2017 [cited by applicant]
US 9673294B2 · Tschumakow et al. · 2017 [cited by applicant]
US 9812369B2 · Hoffmann et al. · 2017 [cited by applicant]
US 10115810B2 · Liu et al. · 2018 [cited by applicant]
US 10186605B1 · Gauthier · 2019 [cited by examiner]
US 10211090B2 · Stamper et al. · 2019 [cited by applicant]
US 10224423B1 · Gauthier · 2019 [cited by examiner]
US 10312356B1 · Liu et al. · 2019 [cited by applicant]
US 10707336B1 · Hashemi · 2020 [cited by examiner]
US 10818772B2 · Jain et al. · 2020 [cited by applicant]
US 11063139B2 · Jain et al. · 2021 [cited by applicant]
US 11145741B2 · Gauthier · 2021 [cited by examiner]
US 11362201B1 · McTaggart et al. · 2022 [cited by applicant]
US 12342555B1 · Raghunathan et al. · 2025 [cited by applicant]
US 20010017399A1 · Oda et al. · 2001 [cited by applicant]
US 20030109109A1 · Freeman · 2003 [cited by examiner]
US 20040256635A1 · Saitoh et al. · 2004 [cited by applicant]
US 20050199907A1 · Divakaruni · 2005 [cited by examiner]
US 20080179632A1 · Adam et al. · 2008 [cited by applicant]
US 20100187657A1 · Boeck · 2010 [cited by examiner]
US 20110198671A1 · Boccardi · 2011 [cited by examiner]
US 20130214275A1 · Adkisson et al. · 2013 [cited by applicant]
US 20140151852A1 · Adkisson · 2014 [cited by examiner]
US 20150008558A1 · Harame et al. · 2015 [cited by applicant]
US 20150137185A1 · Camillo-Castillo et al. · 2015 [cited by applicant]
US 20150137186A1 · Leidy et al. · 2015 [cited by applicant]
US 20160190292A1 · Adkisson et al. · 2016 [cited by applicant]
US 20210036122A1 · Wong · 2021 [cited by examiner]
US 20210257454A1 · Adusumilli · 2021 [cited by examiner]
US 20210273082A1 · Brezza · 2021 [cited by examiner]
US 20230131166A1 · Kirchgessner et al. · 2023 [cited by applicant]
US 20230187527A1 · John · 2023 [cited by examiner]
US 20230230877A1 · Chung · 2023 [cited by examiner]
US 20240079473A1 · John et al. · 2024 [cited by applicant]
US 20250120144A1 · Raghunathan et al. · 2025 [cited by applicant]
DE 10042343A1 · 2002 [cited by applicant]
DE 102015208133B3 · 2016 [cited by applicant]
EP 4235796A1 · 2023 [cited by applicant]
Nguyen et al., “Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation,” ECS Journal of Solid State Science and Technology, 7(10) P588-594, 2018, 4 pages. [cited by applicant]
Pekarik et al., “A 90nm SiGe BiCMOS Technology for mm-wave and high-performance analog applications,” IEEE 2014, downloaded from IEEE Xplore on Sep. 10, 2024, 4 pages. [cited by applicant]
Vu et al., “Advanced Si/SiGe HBT architecture for 28-nm FD-SOI BiCMOS,” IEEE 2016, downloaded from IEEE Xplore on Sep. 10, 2024, 4 pages. [cited by applicant]
Knoops et al., “Status and prospects of plasma-assisted atomic layer deposition,” Research Article, Journal of Vacuum Science and Technology A 37, Mar. 18, 2019, 27 pages. [cited by applicant]
Mitchell, “The Role of the Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) in Mobile Technology Platforms,” Army Research Laboratory, ARL-TN-0459, Sep. 2011, 38 pages. [cited by applicant]
Jagannathan et al., “Self-Aligned SiGe NPN Transistors With 285 GHz fMAX and fT in a Manufacturable Technology,” IEEE Electron Device Letters, vol. 23, No. 5, May 2002, pp. 258-260. [cited by applicant]
U.S. Appl. No. 18/481,632, filed Oct. 5, 2023, 47 pages. [cited by applicant]
U.S. Appl. No. 18/751,428, filed Jun. 24, 2024, 41 pages. [cited by applicant]
U.S. Appl. No. 18/905,278, filed Oct. 3, 2024, 47 pages. [cited by applicant]
U.S. Appl. No. 18/967,735, filed Dec. 4, 2024, 44 pages. [cited by applicant]
U.S. Appl. No. 19/045,068, filed Feb. 4, 2025, 60 pages. [cited by applicant]
U.S. Appl. No. 19/086,225, filed Mar. 21, 2025, 52 pages. [cited by applicant]
European Search Report for corresponding EP Application No. 24217336.7-1211 dated May 20, 2025, 9 pages. [cited by applicant]
U.S. Appl. No. 19/303,461 Application as Filed on Aug. 19, 2025, 47 pages. [cited by applicant]
European Search Report for corresponding EP Application No. 25168190.4-1211 dated Sep. 15, 2025, 11 pages. [cited by applicant]