Low parasitic capacitance contact structure
Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.
1 . A semiconductor device, comprising:
a gate structure disposed over a channel region of an active region and comprising a gate dielectric layer and a metal layer;
a source/drain contact disposed over a source/drain region of the active region;
a pair of spacers extending along sidewalls of the gate structure;
a pair of liners extending along sidewalls of the source/drain contact;
a gate cap layer disposed over and interfacing top surfaces of the gate dielectric layer and the metal layer and sandwiched between the pair of spacers;
a first dielectric feature disposed over the gate cap layer and sandwiched between the pair of spacers;
a source/drain cap layer disposed over the source/drain contact and sandwiched between the pair of liners;
a second dielectric feature disposed over the source/drain cap layer;
a gate contact via extending through the first dielectric feature to contact a surface of the gate cap layer; and
a source/drain contact via extending through the second dielectric feature to contact the source/drain contact.
2 . The semiconductor device of claim 1 ,
wherein the pair of spacers and pair of liners comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxy-carbide, silicon carbide nitride, silicon oxy-carbide nitride, or amorphous silicon,
wherein the first dielectric feature and second dielectric feature comprise silicon, oxygen, nitrogen, or carbon.
3 . The semiconductor device of claim 1 , further comprising:
a second spacer sandwiched between one of the pair of the spacers and one of the pair of liners.
4 . The semiconductor device of claim 3 , wherein the second spacer comprises aluminum oxide, aluminum oxynitride, aluminum nitride, zirconium oxide, zirconium aluminum oxynitride, or a combination thereof.
5 . The semiconductor device of claim 3 , wherein the first dielectric feature is in contact with the second spacer.
6 . The semiconductor device of claim 1 ,
wherein top surfaces of the gate contact via, the pair of spacers and the first dielectric feature are coplanar,
wherein top surfaces of the source/drain contact via, the pair of liners and the second dielectric feature are coplanar.
7 . The semiconductor device of claim 6 , further comprising:
at least one second air pocket disposed in the second dielectric feature and sandwiched between the gate contact via and one of the pair of spacers.
8 . The semiconductor device of claim 1 , further comprising:
at least one first air pocket disposed in the first dielectric feature and sandwiched between the gate contact via and one of the pair of spacers.
9 . The semiconductor device of claim 1 , wherein the gate dielectric layer comprises HfO 2 , TiO 2 , FRO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , or combinations thereof.
10 . The semiconductor device of claim 1 , wherein the source/drain cap layer comprises W, Co, Ni, Ru, Ti, Ta, TiN, TaN, or a combination thereof.
11 . A semiconductor device, comprising:
a gate structure disposed over a channel region of an active region, the gate structure comprising a gate dielectric layer and a gate electrode over the gate dielectric layer;
a source/drain contact disposed over a source/drain region of the active region;
a pair of spacers extending along sidewalls of the gate structure;
a pair of liners extending along sidewalls of the source/drain contact;
a gate cap layer disposed over top surfaces of the gate dielectric layer and the gate electrode and sandwiched between the pair of spacers;
a first dielectric feature disposed over the gate cap layer and between the pair of spacers;
a source/drain cap layer disposed over the source/drain contact and sandwiched between the pair of liners;
a second dielectric feature disposed over the source/drain cap layer and between the pair of liners; and
a first air pocket trapped in the first dielectric feature,
wherein the gate cap layer comprises a conductive material,
wherein a sidewall of the source/drain cap layer is spaced apart from one of the pair of spacers by one of the pair of liners.
12 . The semiconductor device of claim 11 , further comprising:
a second air pocket trapped in the second dielectric feature.
13 . The semiconductor device of claim 11 , wherein a top portion of the first dielectric feature spans over top surfaces of the pair of spacers.
14 . The semiconductor device of claim 11 , wherein a top portion of the second dielectric feature spans over top surfaces of the pair of liners.
15 . The semiconductor device of claim 11 , wherein the first dielectric feature and the second dielectric feature comprise a dielectric constant smaller than 4.
16 . The semiconductor device of claim 11 , wherein the source/drain cap layer comprises W, Co, Ni, Ru, Ti, Ta, TiN, TaN, or a combination thereof.
17 . A semiconductor structure, comprising:
an active region having a channel region and a source/drain region;
a gate cut feature disposed over the channel region and comprising a first low-k dielectric feature;
a source/drain isolation feature disposed over the source/drain region and comprising a second low-k dielectric feature;
a pair of spacers extending along sidewalls of the first low-k dielectric feature;
a pair of liners extending along sidewalls of the second low-k dielectric feature;
a first air pocket disposed in the first low-k dielectric feature in the gate cut feature; and
a second air pocket disposed in the second low-k dielectric feature in the source/drain isolation feature,
wherein a first low-k dielectric feature comprises a lower portion and an upper portion over the lower portion,
wherein a width of the upper portion is greater than a width of the lower portion.
18 . The semiconductor structure of claim 17 ,
wherein the pair of spacers and pair of liners comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxy-carbide, silicon carbide nitride, silicon oxy-carbide nitride, or amorphous silicon,
wherein the gate cut feature and the source/drain isolation feature comprise silicon, oxygen, nitrogen, or carbon.
19 . The semiconductor structure of claim 17 , further comprising:
a second spacer sandwiched between one of the pair of the spacers and one of the pair of liners.
20 . The semiconductor structure of claim 19 , wherein the second spacer comprises aluminum oxide, aluminum oxynitride, aluminum nitride, zirconium oxide, zirconium aluminum oxynitride, aluminum nitride, or a combination thereof.