IC structure with interface liner and methods of forming same
Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, such that the doped metal layer overlies the conductive region, the doped metal layer including a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material, the interface liner formed only on sidewalls of the contact opening and in direct contact with the ILD material and only at an interface of the doped metal layer and the ILD material.
1. An integrated circuit (IC) structure comprising:
a transistor structure including: a substrate including a source/drain region, a source/drain silicide positioned on the source/drain region of the substrate, and a gate metal positioned over the substrate;
an inter-level dielectric (ILD) material positioned on the transistor structure, wherein the ILD material includes a contact opening to a selected one of the source/drain silicide or the gate metal of the transistor structure;
a doped metal layer within the contact opening such that the doped metal layer is positioned over and electrically coupled to the selected one of the source/drain silicide or the gate metal, where the doped metal layer includes a first metal; and
an interface liner positioned directly between the doped metal layer and a sidewall of the ILD material,
wherein the interface liner comprises a second metal and the ILD material, and
wherein the interface liner is formed only at an interface of the doped metal layer and the ILD material.
2. The IC structure of claim 1 , wherein the first metal includes cobalt (Co).
3. The IC structure of claim 2 , wherein the second metal includes manganese (Mn).
4. The IC structure of claim 1 , wherein the ILD material includes silicon oxide, and wherein the interface liner includes manganese silicate.
5. The IC structure of claim 1 , wherein the doped metal layer is positioned directly on an upper surface of the source/drain silicide or the gate metal, such that the interface liner is absent from a junction between a lower surface of the doped metal layer and the transistor structure.
6. The IC structure of claim 1 , wherein the interface liner includes a composition formed from the second metal diffused into or reacting with the ILD material.
7. The IC structure of claim 1 , wherein the interface liner is positioned only on sidewalls of the contact opening and in direct contact with the ILD material.