Memory devices and methods of manufacturing thereof
View Patent ↗A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.
1 . A method for fabricating a semiconductor device, comprising:
forming a fin-based structure protruding from a top boundary of a substrate, wherein the fin-based structure is made of a first semiconductor material;
forming a nanosheet-based structure protruding from the top boundary of the substrate, wherein the nanosheet-based structure includes one or more first nanosheets, made of a second semiconductor material, and one or more second nanosheets, made of the first semiconductor material, the one or more first nanosheets and the one or more second nanosheets being alternatingly disposed with respect to each other; and
epitaxially growing a first source/drain (S/D) region, a second S/D region, and a third S/D region, wherein the first S/D region is disposed between and directly connects the fin-based structure and the nanosheet-based structure, the second S/D region is disposed opposite the fin-based structure from the first S/D region, and the third S/D region is disposed opposite the nanosheet-based structure from the first S/D region, and wherein the first to third S/D regions have a same conductive type,
wherein sidewalls of the fin-based structure each have a first crystal plane, and a top boundary and a bottom boundary of each of the one or more first nanosheets have a second crystal plane, and wherein the first crystal plane includes a {110} crystal plane, and the second crystal plane incudes a {100} crystal plane.
2 . The method of claim 1 , further comprising:
forming a first gate structure straddling the fin-based structure;
removing the one or more second nanosheets; and
forming a second gate structure wrapping around each of the one or more first nanosheets.
3 . The method of claim 2 , wherein the first gate structure, the fin-based structure, the first S/D region, and the second S/D region collectively operate as a programming transistor of an anti-fuse memory cell, and the second gate structure, the one or more first nanosheets, the second S/D region, and the third S/D region collectively operate as a reading transistor of the anti-fuse memory cell.
4 . The method of claim 3 , wherein the reading transistor is electrically coupled to the programming transistor in series via the second S/D region.
5 . The method of claim 1 , wherein sidewalls of the fin-based structure each have a first crystal plane, a top boundary and a bottom boundary of each of the one or more first nanosheets have a second crystal plane, and a top boundary and a bottom boundary of each of the one or more third nanosheets have the second crystal plane, and wherein the first crystal plane includes a {110} crystal plane, and the second crystal plane incudes a {100} crystal plane.
6 . The method of claim 1 , wherein the fin-based structure and the one or more first nanosheets all extend along a same physical direction.
7 . The method of claim 1 , further comprising forming inner spacers adjacent the one or more second nanosheets prior to forming the second S/D region, wherein the inner spacers comprise a dielectric material different from the first and second semiconductor materials.
8 . The method of claim 1 , further comprising:
forming the fin-based structure in a first region of the substrate;
forming a recess in a second region of the substrate; and
forming the nanosheet-based structure in the recess.
9 . The method of claim 8 , further comprising:
covering the fin-based structure with a blocking mask while etching respective end portions of each of the one or more second nanosheets; and
forming a pair of inner spacers in contact with each of the one or more etched second nanosheets.
10 . The method of claim 8 , wherein forming the recess in the second region comprises:
depositing a dielectric liner along sidewalls of the recess; and
performing an anisotropic etch to remove horizontal portions of the dielectric liner while retaining vertical portions.
11 . A method for fabricating a memory device, comprising:
forming a first transistor in a first region of a substrate, wherein the first transistor includes:
a fin-based structure extending along a first physical direction;
a first gate structure extending along a second physical direction and straddling the fin-based structure, the second physical direction being perpendicular to the first physical direction;
a first source/drain (S/D) region disposed on a first side of the first gate structure along the first physical direction; and
a second S/D region disposed on a second side of the first gate structure along the first physical direction; and
forming a second transistor in a second region of the substrate adjacent the first region along the first physical direction, wherein the second transistor includes:
a plurality of nanosheets extending along the first physical direction, wherein the plurality of nanosheets are formed by alternatingly stacking layers of a first semiconductor material and a second semiconductor material;
a second gate structure extending along the second physical direction and wrapping around each of the plurality of nanosheets;
the second S/D region which is on a first side of the second gate structure along the first physical direction and directly connects the fin-based structure of the first transistor to the plurality of nanosheets of the second transistor;
a third S/D region on a second side of the second gate structure along the first physical direction; wherein the first to third S/D regions have a same conductive type,
wherein sidewalls of the fin-based structure each have a first crystal plane, and a top boundary and a bottom boundary of each of the nanosheets have a second crystal plane.
12 . The method of claim 11 , wherein the first transistor operatively functions as a programming transistor of an anti-fuse memory cell, and the second transistor operatively functions as a reading transistor of the anti-fuse memory cell.
13 . The method of claim 11 , wherein the fin-based structure has a first width (W 2 ) along the second physical direction and each of the plurality of nanosheets has a second width (W 1 ) along the second physical direction, wherein W 1 >W 2 .
14 . A method for fabricating a semiconductor device, comprising:
forming, in a first region of a substrate, a fin-based structure vertically extending away from the substrate and laterally extending along a first physical direction;
forming, in a second region of the substrate adjacent the first region along the first physical direction, a recess;
forming, in the recess, a nanosheet-based structure, wherein the nanosheet-based structure includes a number of first nanosheets and a number of second nanosheets alternatingly arranged on top of one another;
forming a first source/drain (S/D) region in contact with a first end of the fin-based structure;
forming a second S/D region in contact with a second end of the fin-based structure and also in contact with a first end of each of the first nanosheets;
forming a third S/D region in contact with a second end of each of the first nanosheets;
forming a first gate structure, interposed between the first and second S/D regions, that straddles the fin-based structure; and
forming a second gate structure, interposed between the second and third S/D regions, that wraps around each of the first nanosheets;
wherein the first to third S/D regions have a same conductive type,
wherein sidewalls of the fin-based structure, facing toward or away from a second physical direction perpendicular to the first physical direction, each has a {110} crystal plane, and a top boundary and a bottom boundary of each of the first nanosheets have a {100} crystal plane.
15 . The method of claim 14 , further comprising removing the second nanosheets before forming the second gate structure.
16 . The method of claim 14 , wherein sidewalls of the fin-based structure each have a first crystal plane, and a top boundary and a bottom boundary of each of the one or more first nanosheets have a second crystal plane.
17 . The method of claim 14 , further comprising:
covering the fin-based structure with a blocking mask while etching respective end portions of each of the one or more second nanosheets; and
forming a pair of inner spacers in contact with each of the one or more etched second nanosheets.
18 . The method of claim 14 , wherein the first gate structure, the fin-based structure, the first S/D region, and the second S/D region collectively operate as a programming transistor of an anti-fuse memory cell, and the second gate structure, the one or more first nanosheets, the second S/D region, and the third S/D region collectively operate as a reading transistor of the anti-fuse memory cell.
19 . The method of claim 14 , wherein the fin-based structure and the one or more first nanosheets all extend along a same physical direction.
20 . The method of claim 14 , Wherein forming the second gate structure comprises depositing a gate dielectric containing hafnium oxide (HfO 2 ) that directly contacts top, bottom, and side surfaces of each first nanosheet.