Granted Patent B2

US 12,464,956 · App. 18/122,165 · Granted Nov 4, 2025

Inventors: Hui-Lin Wang (Taipei, TW); Che-Wei Chang (Taichung, TW); Ching-Hua Hsu (Kaohsiung, TW); Chen-Yi Weng (New Taipei, TW); Po-Kai Hsu (Tainan, TW)

Assignee: UNITED MICROELECTRONICS CORP.

H10N50/10H01L23/5226H01L23/5283H10B61/00H10N50/80

Abstract

Claims (38)

1 . A magnetic random access memory structure, comprising:

a substrate;

a first dielectric layer disposed on the substrate;

a first conductive via and a second conductive via in proximity to the first conductive via embedded in the first dielectric layer;

a bottom electrode layer disposed on the first dielectric layer, wherein the bottom electrode layer electrically connects the first conductive via with the second conductive via;

a spin orbit coupling layer disposed on the bottom electrode layer;

a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer;

a top electrode layer disposed on the MTJ element;

a nitride protective layer surrounding the MTJ element and the top electrode layer, and the nitride protective layer masking the spin orbit coupling layer;

an oxide mask layer surrounding the nitride protective layer;

a nitride spacer layer surrounding the oxide mask layer and the nitride protective layer; and

a second dielectric layer surrounding the nitride spacer layer.

2 . The magnetic random access memory structure according to claim 1 , wherein the MTJ element comprises a free layer in direct contact with the spin orbit coupling layer, a tunnel barrier layer on the free layer, and a reference layer on the tunnel barrier layer.

3 . The magnetic random access memory structure according to claim 2 , wherein the MTJ element further comprises a cap layer on the reference layer, wherein the top electrode layer is disposed on the cap layer.

4 . The magnetic random access memory structure according to claim 1 , wherein the oxide mask layer between the nitride protective layer and the nitride spacer layer has a first thickness in a first direction and a second thickness in a second direction, wherein the first thickness is different from the second thickness.

5 . The magnetic random access memory structure according to claim 1 , wherein the nitride protective layer comprises silicon nitride, the oxide mask layer comprises silicon oxide, and the nitride spacer layer comprises silicon nitride.

6 . The magnetic random access memory structure according to claim 1 , wherein the nitride spacer layer is in direct contact with a peripheral sidewall of the nitride protective layer, a peripheral sidewall of the spin orbit coupling layer, and a peripheral sidewall of the bottom electrode layer.

7 . The magnetic random access memory structure according to claim 1 , wherein the nitride spacer layer is in direct contact with the first dielectric layer.

8 . The magnetic random access memory structure according to claim 1 , wherein a top surface of the second dielectric layer is coplanar with a top surface of the nitride spacer layer, a top surface of the oxide mask layer, a top surface of the nitride protective layer, and a top surface of the top electrode layer.

9 . The magnetic random access memory structure according to claim 1 , wherein the spin orbit coupling layer comprises a tungsten layer.

10 . A magnetic random access memory structure, comprising:

a first dielectric layer;

a bottom electrode layer disposed on the first dielectric layer;

a spin orbit coupling layer disposed on the bottom electrode layer;

a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer;

a top electrode layer disposed on the MTJ element;

a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer;

a mask layer surrounding the protective layer;

a spacer layer surrounding the mask layer and the protective layer; and

a second dielectric layer surrounding the spacer layer.

11 . The magnetic random access memory structure according to claim 10 , wherein the MTJ element comprises a free layer in direct contact with the spin orbit coupling layer, a tunnel barrier layer on the free layer, and a reference layer on the tunnel barrier layer.

12 . The magnetic random access memory structure according to claim 11 , wherein the MTJ element further comprises a cap layer on the reference layer, wherein the top electrode layer is disposed on the cap layer.

13 . The magnetic random access memory structure according to claim 10 , wherein the mask layer between the protective layer and the spacer layer has a first thickness in a first direction and a second thickness in a second direction, wherein the first thickness is different from the second thickness.

14 . The magnetic random access memory structure according to claim 10 , wherein the protective layer comprises silicon nitride, the mask layer comprises silicon oxide, and the spacer layer comprises silicon nitride.

15 . The magnetic random access memory structure according to claim 10 , wherein the spacer layer is in direct contact with a peripheral sidewall of the protective layer, a peripheral sidewall of the spin orbit coupling layer, and a peripheral sidewall of the bottom electrode layer.

16 . The magnetic random access memory structure according to claim 10 , wherein the spacer layer is in direct contact with the first dielectric layer.

17 . The magnetic random access memory structure according to claim 10 , wherein a top surface of the second dielectric layer is coplanar with a top surface of the spacer layer, a top surface of the mask layer, a top surface of the protective layer, and a top surface of the top electrode layer.

18 . The magnetic random access memory structure according to claim 10 , wherein the spin orbit coupling layer comprises a tungsten layer.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (10)